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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
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Old 16th June 2012, 10:26 AM   #661
marce is offline marce  United Kingdom
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
When doing boards, the clock is always the most critical signal, so placement is always done so that any clock traces are the shortest routes on the board. This is one of the major rules for digital PCB design, whotever the system. So you will always get the best results with the shortest clock. Remote clocks can be done but you have to be careful with the interface, ie how you get the clock signal from the xtal to the IC clock input pins.
Personaly I have never done a board where the main clock is remote from the main circtuitry, apart from some bus systems where you have system clocks running around, though these tend to be on motherboards.
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Old 17th June 2012, 02:52 AM   #662
tjencks is offline tjencks  United States
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Thanks Marce,

That is what I seem to recall from the reading I've done on Buff III. I know that Ian has some sort of adapter board for the Buff III built which no doubt will give the shortest leads but not sure how many he has or if he is still offering them. In any case at this point it is certainly not possible to achieve a shorter lead length than the Buff III's built in clock. So short lead length vs. your I2S source running on the same clock as the DAC with the FIFO. Wonder if anyone has done an jitter measurement on the two. It would seem that the FIFO route despite the lead length is more advantageous and thus I would suspect lower jitter than the alternative, judging from folks comments on the sonic improvements of the FIFO.

-TJ
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Old 17th June 2012, 06:09 AM   #663
Blitz is offline Blitz  Germany
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one question...what is the best practise to get i2s from the pc ? usb or directly fro, the sound card like a julia ? or other method ?
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Old 17th June 2012, 06:27 AM   #664
qusp is offline qusp  Australia
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USB, unless you can mount the juli@ right next to the dac somehow. using i2s over distances to connect boxes is nothing but hype, its not designed for long connections and anything that makes it able to adds jitter
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Old 17th June 2012, 06:58 AM   #665
regal is offline regal  United States
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How is it going with the L/R splitter board? If we aren't going to split the data into left and right via the software, what is the opinion of something like this added to the front of the reclocking board with jumpers and of course an extra reclocking of the extra data line? It would help those wanting to use good dac chips for NOS and or oversampling via computer:

Click the image to open in full size.

Just a snapshot of what this would enable the use of:

DAC THD&N SNR
AD1865 - 88dB -110dB
AD1862 - 98dB -119dB
PCM56 - 94dB -110dB
PCM63K -1000dB -120dB
PCM1702K -100dB -110dB
PCM1704K -101dB -120dB

Last edited by regal; 17th June 2012 at 07:01 AM.
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Old 17th June 2012, 07:52 AM   #666
dddac is offline dddac  Germany
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Default max Clock Speed of CD4xxx

did you actually built this? the max clock speed of these series should be an issue for anything above 44.1 Fs. even this might prove to be an issue. with 74HC164 it works up to 192kHz Fs (I built this)
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Old 17th June 2012, 08:15 AM   #667
regal is offline regal  United States
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The last I read on this thread is the splitting/shifting would be hardware rather than software, hence why I brought it up (limited fs.) Did you like the 74C164 version?
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Old 17th June 2012, 02:33 PM   #668
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by bigpandahk View Post
I prefer I2S which sounds better.
S/PDIF, as well as AES/EBU, transmits both clock and data signals at same time with bi-phase modulation, which will introduce more jitter during clock recovery on receiver side by a normal DIR chip. The recovery clock is generated and has to track the bi-phase signal to avoid un-locking. That's why you prefer I2S.

But it's no longer an issue if you put a FIFO between the DIR and DAC. I did a loop testing (big loop) on my DIX9211 S/PDIF board and confirmed that the S/PDIF transmiting is bit-perfect for I2S stream below 24bit. That meas there is no difference between I2S and S/PDIF as inputs for FIFO applications except you need real 32bit I2S. The MAX Fs would be a real limitation for a S/PDIF.

Different from S/PDIF, I2S is not an isolated transmiting, which obviously introducing EMI noise via ground or ground loop. Another problem is, TTL was not designed for distance transmiting. So, for I2S applications, I'm highly recommending using logic isolate chips, and making the cables as short as possible(or converting them into LVDS).

Is there anybody has ever tried NVE IL7XX digital isolators or other digital isolating solutions for I2S signals?

Have a nice weekend.

Ian

Last edited by iancanada; 17th June 2012 at 02:35 PM.
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Old 17th June 2012, 02:54 PM   #669
bigpandahk is offline bigpandahk  Hong Kong
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Quote:
Originally Posted by iancanada View Post
That meas there is no difference between I2S and S/PDIF as inputs for FIFO applications except you need real 32bit I2S. The MAX Fs would be a real limitation for a S/PDIF.

Ian
Thanks Ian, I will connect the WaveIO to the TTL SPDIF input of FIFO. One question about source selection, do I have to use a relay to short the selection header or just feed a TTL "Low" to the pin?
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Old 17th June 2012, 03:22 PM   #670
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by bigpandahk View Post
Thanks Ian, I will connect the WaveIO to the TTL SPDIF input of FIFO. One question about source selection, do I have to use a relay to short the selection header or just feed a TTL "Low" to the pin?
I don't see any problem if you keep TTL low for no-selected signals, except the souce ground is too noisy. But the FIFO board doesn't have a spdif input, you have to feed it into the ttl input of the spdif board.

Regards,

Ian
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