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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
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Old 7th September 2018, 03:36 PM   #4691
wtnh is offline wtnh  United States
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Quote:
Originally Posted by Markw4 View Post
It could be that 1/f noise at low audio frequencies could be one of the biggest problems with RF LDOs and sound quality. In either the LT3045 or LT3042 data sheet, one of them, there is a suggested application circuit that uses an LTC6655 to improve the LF noise issue. Probably better than only increasing Cset. Also, although graphs of noise density at individual frequencies may look very good, we really should be thinking in terms of integrated noise over the frequency band that could affect sound quality for a given type of circuitry.
Yes - that shows up in the LT3042 datasheet. They mention taking Cset as high as 22uF to minimize LF noise. The LTC6655 is a relatively expensive part, and improvements would probably be swamped by poor PCB layput, lack of multi-layer (>2) boards, etc. At these levels, pretty sophisticated measurement techniques would be required to detect differences. I think that is why Iancanada is recommending an ultracap or LifoPO4 supply.

Cheers

Whit
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Old 7th September 2018, 04:10 PM   #4692
darioia is offline darioia
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Originally Posted by fralippo View Post
Is it possible to feed +5V to the Raspberry thru power connector on RPi I2S cap PCB? I'd be happy not to use that micro-usb, or whatever it is, standard cable.

Hi, my Chinese Dac powered with 12V send power at an DC/DC converter to 5V ant send it at my RPI via RPI Main Connector, the RPI converts this power in 3.3 V (stabilise/filtered) and use that power for the system.


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Old 7th September 2018, 05:49 PM   #4693
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by Markw4 View Post
It could be that 1/f noise at low audio frequencies could be one of the biggest problems with RF LDOs and sound quality. In either the LT3045 or LT3042 data sheet, one of them, there is a suggested application circuit that uses an LTC6655 to improve the LF noise issue. Probably better than only increasing Cset. Also, although graphs of noise density at individual frequencies may look very good, we really should be thinking in terms of integrated noise over the frequency band that could affect sound quality for a given type of circuitry.
@Markw4

Totally agree with you. That's why I recommended the direct 3.3V ultra capacitor power supply or 3.3V LifePO4 power supply without any LDO involved.

People was more interested in the noise uV numbers, however the 1/f noise was overlooked.

Regards,
Ian
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Old 8th September 2018, 08:17 PM   #4694
niner is offline niner  United States
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Ian, is it possible to provide a world clock input for FIFO, which is to be used for synchronous multiple audio devices?
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Old 8th September 2018, 08:37 PM   #4695
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
@niner;

It is possible making the FIFO output as world clock.

Ian
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Old 8th September 2018, 08:43 PM   #4696
niner is offline niner  United States
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Originally Posted by iancanada View Post
@niner;

It is possible making the FIFO output as world clock.

Ian
Umm, having a world clock as input of FIFO would be very useful for me. That way I can sync multiple FIFO boards with the same world clock.

(you and I talked about it a little bit over email)
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Old 10th September 2018, 03:23 AM   #4697
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Default FifoPi with Buffalo-IIIse

Twisted Pear's new DACs have MCLK input. That makes it very easy to run them at sync clock mode to improve sound quality. The connections between FifoPi and Buffalo-IIIse are very straight forward, just four u.fl coaxial cables. Looks very clean.

I also started an all in one LifePO4 power supply project for this kind of applications. Hopefully I can put them working together very soon. I'll have more update then.
Develop ultra capacitor power supply and LiFePO4 battery power supply


Click the image to open in full size.
FifoPi_BuffaloIIISE
by Ian, on Flickr

Ian
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Old 23rd September 2018, 07:27 PM   #4698
franz159 is offline franz159
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Quote:
Originally Posted by iancanada View Post
FifoPi makes ES9038Q2M DAC HAT working at pure sync clock mode. The MCLK u.fl cable is the only cable that needs to be connected for sound quality. Anything else will be plug and play.

ESS controller can be connected to the non-isolated GPIO of the FifoPi. I'm highly rerecorded doing it this way. With the FifoPi on-board isolator, ESS controller will be 100% isolated from ES9038Q2M DAC in this case. The processor of the controller will never have any galvanic impact to the DAC.

.....

Ian
Interested and following!
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Old 28th September 2018, 12:40 PM   #4699
hellokitty123 is offline hellokitty123  United States
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Hi, I had to reassemble my Fifo and I forget which pin is "slen".
Manual says I need to drive the "slen" pin high in order to activate slave mode but none of the pins are labels slen in the manual.
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Old 30th September 2018, 12:59 AM   #4700
hellokitty123 is offline hellokitty123  United States
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Anyone?
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