I have an soekris 1021 with i2s input.but dont know why to have sound i need to turn on eq or resampling in roon audio. Orginal 16 or 24bit dont work. Soekris Audio ApS, Products dam1021
By default FifoPi will follow the original format. But I don't know what was the original format. To address this issue, you need to monitor the real format?
Do you have my ESS controller? You can run it at analyzer mode to watch the format at real time. If would be great too to debug a digital audio system.
Regards,
Ian
If you had my ESS controller you can check the real format, unless you have a oscilloscope.
FifoPi support native DSD mode, so it works for HQplayer. But maybe you will need a BridgePi because a RPi doesn't support native DSD through GPIO, have to use a USB streamer like a Amanero Combo384.
Regards,
Ian
Hi Ian, this was a nice confirmation, but I am still curious and very much looking forward to, if you also did the measurement after the Fifopi ? with standard and top notch clocks?
"domestic jitter (the two groups) is separated 1200ps in between, looks like that RaspberryPi internal DPLL jumps between two factors for the audio clock"... Is this what seems to be called MASH?
Raspberry Pi Clock jitter and MASH value - YouTube
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Raspberry Pi Clock jitter and MASH value - YouTube
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FifoPi jitter test: (3) S/PDIF receiver jitter before FifoPi
Just got some time so let's continue the jitter test.
Here is jitter testing result of a typical S/PDIF receiver, AK4113, with RCA 75 ohm coaxial cable input @44.1KHz music
The first graph is the output MCLK jitter: 45.7ps (3ps jitter measurement noise floor was excluded), which is not bad among all DIR chips. MCLK runs at 5.6448MHz or 128Fs
The second graph is the output SCK jitter: 79.6ps which is a bit higher than I thought. I think AK4113 didn't re-clock signals before outputting I2S. However it's not a big deal if the DAC works in sync mode (with MCLK input).
The third graph is the jitter observation directly from the SCK waveform on my digital scope screen. Only random jitter, no domestic jitter. Seems with analog PLL only.
You can get them compared with jitter test result of a RPi
https://www.diyaudio.com/forums/dig...mate-weapon-fight-jitter-533.html#post6284897
https://www.diyaudio.com/forums/dig...mate-weapon-fight-jitter-539.html#post6290977
Overall, this S/PDIF receiver signal quality is better than the I2S signal from a RPi GPIO. However, to reach a higher audiophile standard, neither of them is acceptable.
SPDIF_MCLK_Jitter_RCA by Ian, on Flickr
SPDIF_SCK_Jitter_44.1KHz_32Bit_RCA by Ian, on Flickr
SPDIF_SCK_Jitter_44.1KHz_32Bit_Waveform_RCA by Ian, on Flickr
Ian
Just got some time so let's continue the jitter test.
Here is jitter testing result of a typical S/PDIF receiver, AK4113, with RCA 75 ohm coaxial cable input @44.1KHz music
The first graph is the output MCLK jitter: 45.7ps (3ps jitter measurement noise floor was excluded), which is not bad among all DIR chips. MCLK runs at 5.6448MHz or 128Fs
The second graph is the output SCK jitter: 79.6ps which is a bit higher than I thought. I think AK4113 didn't re-clock signals before outputting I2S. However it's not a big deal if the DAC works in sync mode (with MCLK input).
The third graph is the jitter observation directly from the SCK waveform on my digital scope screen. Only random jitter, no domestic jitter. Seems with analog PLL only.
You can get them compared with jitter test result of a RPi
https://www.diyaudio.com/forums/dig...mate-weapon-fight-jitter-533.html#post6284897
https://www.diyaudio.com/forums/dig...mate-weapon-fight-jitter-539.html#post6290977
Overall, this S/PDIF receiver signal quality is better than the I2S signal from a RPi GPIO. However, to reach a higher audiophile standard, neither of them is acceptable.
SPDIF_MCLK_Jitter_RCA by Ian, on Flickr
SPDIF_SCK_Jitter_44.1KHz_32Bit_RCA by Ian, on Flickr
SPDIF_SCK_Jitter_44.1KHz_32Bit_Waveform_RCA by Ian, on Flickr
Ian
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So if I am just using the McFIFO, how do I connect to the receiver pi and the transport pi?
Do I just connect the bit clock, word clock, and data to the u.fl connectors on the TransportPI and the masterclock from the McFIFO to the transportPI mclk u.fl connector? Which mclk connection do I use on the McFIFO? Do I need an isolator between the receiverPI and the TransportPi or anywhere else?
Do I just connect the bit clock, word clock, and data to the u.fl connectors on the TransportPI and the masterclock from the McFIFO to the transportPI mclk u.fl connector? Which mclk connection do I use on the McFIFO? Do I need an isolator between the receiverPI and the TransportPi or anywhere else?