Is there really any difference between ASRCs (like TI SRC4193/4) and Oversampling Digital Filters (like NPC SM5842/7) in the way they do integer (4x,8x) oversampling ?
I suppose it would be possible to set a integer Fsout/Fsin ratio in an ASRC ? And in that case, is there any difference in the way it accomplishes the oversampled output, as compared to a filter that is a "4x/8x oversampling digital filter" ?
One more question about OS DFs -
Typically they utilize a stepped approach to oversample, so if you wanted 8x oversampling they would first oversample to 2x, then they would oversample that result into 4x and then repeat the same exercise to get 8x. Basically use the result of the previous step as an input to the next step. Now I can understand why they might do that. They might want to make it flexible so the user can use any ratio they want, and it also seems like this method is less demanding in terms of processing power. BUT, my question is -
if there was ample processing power at your disposal, and 8x was the only ratio desired, then would the results(distortion, noise) of doing 8x oversampling at one shot be any different than doing the oversampling in three steps ?
I suppose it would be possible to set a integer Fsout/Fsin ratio in an ASRC ? And in that case, is there any difference in the way it accomplishes the oversampled output, as compared to a filter that is a "4x/8x oversampling digital filter" ?
One more question about OS DFs -
Typically they utilize a stepped approach to oversample, so if you wanted 8x oversampling they would first oversample to 2x, then they would oversample that result into 4x and then repeat the same exercise to get 8x. Basically use the result of the previous step as an input to the next step. Now I can understand why they might do that. They might want to make it flexible so the user can use any ratio they want, and it also seems like this method is less demanding in terms of processing power. BUT, my question is -
if there was ample processing power at your disposal, and 8x was the only ratio desired, then would the results(distortion, noise) of doing 8x oversampling at one shot be any different than doing the oversampling in three steps ?
Hi percy,
From the datasheet, the SRC4192/3 is a conventional 16x-oversampler, followed by a *resampler* and then a conventional (adjustable?) decimator. It doesn't say in the datasheet quite how the resampler works, but I would imagine it to be based on some sort of polynomial interpolation process.
As for the question of which method is best, it's really hard to say. I designed a few filters quickly in MATLAB (one 600-tap 8x oversampling filter and 3 polyphase 2x filters (150-tap, 20-tap and 16-tap) for cascading). I was pretty quick in the designs, but aimed for minimal passband ripple, minimal attenuation at 20kHz and 120-dB stopband attenuation. Overall, the responses of the two approaches in both frequency- and time-domain looked very similar. I would suggest that the 8x filter is somewhat less fiddly to design, but then you're looking at 600 MACs/sample as opposed to about 90 MACs/sample for the cascaded approach. Not really worth the simplicity on that front
To be practical, the cascaded approach would need a quantisation after each filter, as opposed to one single quantisation after the 8x filter, so there'd be 3 times as much quantisation noise in the cascaded version. If you use long enough word-lengths to begin with though, and dither at each truncation (see my many rants on dither on this forum if you don't know about it), then this is a non-issue.
If I were designing an oversampler, I'd not really be able to justify to myself the extra expense of the single-filter solution, even if I had the computing power. The gains just aren't there.
From the datasheet, the SRC4192/3 is a conventional 16x-oversampler, followed by a *resampler* and then a conventional (adjustable?) decimator. It doesn't say in the datasheet quite how the resampler works, but I would imagine it to be based on some sort of polynomial interpolation process.
As for the question of which method is best, it's really hard to say. I designed a few filters quickly in MATLAB (one 600-tap 8x oversampling filter and 3 polyphase 2x filters (150-tap, 20-tap and 16-tap) for cascading). I was pretty quick in the designs, but aimed for minimal passband ripple, minimal attenuation at 20kHz and 120-dB stopband attenuation. Overall, the responses of the two approaches in both frequency- and time-domain looked very similar. I would suggest that the 8x filter is somewhat less fiddly to design, but then you're looking at 600 MACs/sample as opposed to about 90 MACs/sample for the cascaded approach. Not really worth the simplicity on that front
To be practical, the cascaded approach would need a quantisation after each filter, as opposed to one single quantisation after the 8x filter, so there'd be 3 times as much quantisation noise in the cascaded version. If you use long enough word-lengths to begin with though, and dither at each truncation (see my many rants on dither on this forum if you don't know about it), then this is a non-issue.
If I were designing an oversampler, I'd not really be able to justify to myself the extra expense of the single-filter solution, even if I had the computing power. The gains just aren't there.
The plain old AD1890 datasheet have some explanation on the principle of ASRC.
Link to AD1890 datasheet
Link to AD1890 datasheet
Wingfeather's reply is the closest to what I was looking for. I understand how sample rate conversion and oversampling works. I am trying to compare the working of an ASRC with an OSDF. Its intuitive to think they would be the same but apparently not.
Wingfeather, I saw the functional block diagram of the SRC4192/3. Would you agree that the SRC4192/3 does a lot more messing around with the data then a straightforward 8x oversampling filter ? Thanks for giving it a try in matlab though, appreciate that. However -
but isn't that what they said for the "1-Bit" Dac too ?
Wingfeather, I saw the functional block diagram of the SRC4192/3. Would you agree that the SRC4192/3 does a lot more messing around with the data then a straightforward 8x oversampling filter ? Thanks for giving it a try in matlab though, appreciate that. However -
you mean out of band noise ?
but isn't that what they said for the "1-Bit" Dac too ?
That's hard to say without knowing specifically how the resampler block works. If it's simply a zero-order hold (i.e. doesn't actually modify any values), and you're working with the SRC4193 (which has the "Direct Down-Sampler" option) then the ASRC appears to consist only of a single FIR oversampling filter. So the two should be the same. If the resampler is more complex than that (such as a linear/polynomial interpolation et al), then I would agree that it does mess more with the data. If your two clock domains are synchronous and you can thus get away with a pure FIR solution, then that's going to be the cleanest approach.
Well no, not really. A lone (dithered) quantiser will produce white quantisation noise. It could be shaped into the stop-band region if a noise-shaping quantiser is used, but on straight FIR filters such as used for oversampling that's not generally the case. There will thus be a white noise floor in the signal coming out of the filter.
With a word length of 32 bits, which is getting more and more common, the noise power from quantisation is of the order of -190dBFS. Having three quantisations (and so three times as much noise power) will degrade this by ~4.77dB - really not a huge problem at this sort of level. So while the quantisation noise is definitely in-band, it's not important provided that enough bits are used.
There are good details of the SRC4192 implementation in the associated patent. Go to:
http://patft.uspto.gov/netahtml/PTO/search-bool.html
and search for patent 7,262,716. The patent itself contains references to prior patents describing the techniques used in the AD1896, etc. and some discussion of differences.
I have a decent background in signal processing but I'd have to sit down for an afternoon to answer the original poster's question with any degree of certainty. On first impression, however, the results should be similar. Given that the SRC4192 has jitter rejection issues (whereas the SRC4392 doesn't), I don't see any point in using the SRC4192 just for its own sake, i.e. if you don't need ASRC. The SRC4392 is a good option, but you need a microcontroller.
http://patft.uspto.gov/netahtml/PTO/search-bool.html
and search for patent 7,262,716. The patent itself contains references to prior patents describing the techniques used in the AD1896, etc. and some discussion of differences.
I have a decent background in signal processing but I'd have to sit down for an afternoon to answer the original poster's question with any degree of certainty. On first impression, however, the results should be similar. Given that the SRC4192 has jitter rejection issues (whereas the SRC4392 doesn't), I don't see any point in using the SRC4192 just for its own sake, i.e. if you don't need ASRC. The SRC4392 is a good option, but you need a microcontroller.
The input to the "resampler" is 16Fsin and the output is 16Fsout, so only when Fsin=Fsout it would be transparent otherwise it would always do something with the data (16*Fsout).
I just took SRC41x as an example, you could very well use the SRC4392 as an example too.
Even though the functional block diagram of the src4392 is not as specific as the src4193's in terms of the input and output of the resampler, the description does say that the final decimation filter does nothing but just 'selects 1 out of 16 samples of the resampler's output' which makes me believe its function is the same in both.
Wodgy, if and when you find any results, please do post here. Although I didn't understand what you said about needing a microcontroller.
I just took SRC41x as an example, you could very well use the SRC4392 as an example too.
Even though the functional block diagram of the src4392 is not as specific as the src4193's in terms of the input and output of the resampler, the description does say that the final decimation filter does nothing but just 'selects 1 out of 16 samples of the resampler's output' which makes me believe its function is the same in both.
Wodgy, if and when you find any results, please do post here. Although I didn't understand what you said about needing a microcontroller.
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