.. the QFN package is not a problem but the CML somehow is. To solve this problem, I'm thinking to use AC coupled LVDS receivers (perhaps little logic gates from TI) wired into CDCL6010's outputs and adapted for CML logic (CML to LVDS). The reference will be one VC(X)O from Crystek.
Any thoughts or ideeas?
Cheers
Unfortunately, it's true... though I was thinking to use the VCXO to feed the PLL synthesizer thus have up to 10 synchronized CML outputs available for various digital circuits used in my future DAC - I hope the losses will be minimal in this way...
It's supposed to have the digital part completely isolated from the analogic one (that's why I want to use differential, AC coupled clock signals). These 10 clock signals should be synchronous with each other so the clock delays on my board should be minimal (the layout will try to reflect that). In addition, the fs and 64-fs clocks will be directly generated by the CDCL6010, so I wouldn't have to use (noisy) external circuits to do divide the master clock signal (CPLDs or FPGAs for example).
I have a good impresion about differential signals in therms of jitter when are properly implemented (good PS and layout, minimal noise). Unfortunately, my project requires to have one low-jitter clock oscillator with multiple outputs. In addition, I need multiple frecv. generated by one (VC)XO to used them with various input sample rates. So, this is what I come so far: XO and PLL synth.
thanx for repply!
Yes, this is one possibility, though I still need 10 Synchronous clocks from the same VCXO with lowest jitter possible and I do need digital domain to be sepparated from the analog one (this is mandatory). I guess this sepparation can be made using AC-coupled differential signaling... so I'm back to the CDCL6010 "problem".
Though, I consider that CPLDs aren't so good for the clock division tasks... a lot of noise from surrounding, on-chip signals.
regards
it will be only a board, perhaps 250 mm. long in the final form though the digital circuitry will take less space. There aren't any cables, only (paired-for differential, same length) PCB tracks. I'll try to keep them as short as possible without using vias. Also, I'll isolate these drivers from the rest of chips (having it's own PS) so CPLD isn't a solution anymore...
thanx
thanx
the DAC uses four PCM1794A chips for a stereo configuration. Every DAC will need three synchronous clock signals: I2S Bit-Clock/Word-Clock and System Clock. Fortunately, there are no ADCs on that board.
A very good ideea though, I must admit, it's an exotic one. Besides that... it would need too many cables/connectors for every DAC chip.
Best regards!
well, in this case we have different opinions about "exotic" implementations.
Excluding the care for PCB layout, I thing that differentialing is still a good approach with good benefits.yes, I'll do that: it's one of the main board's constraints. I'll make a block schematic for better understanding. In the end, I guess that the distance between DACs and clock source is less than 250 mm long.
best
excelon said:
well, in this case we have different opinions about "exotic" implementations.
yes, I'll do that: it's one of the main board's constraints. I'll make a block schematic for better understanding. In the end, I guess that the distance between DACs and clock source is less than 250 mm long.
best
Differential signalling only works as long as the full path is diffeerentiasl. Given all parasitics on biards, that is a ahard job. Coax is much better - been there, done that.
And you "should" place the clock close to the DACs, that is rule number one with DAC design.
best
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