TDA1541 DEM reclocking

Anyone successfully implemented the Henk ten Pierick DEM reclocking for the TDA1541 ?
I've tried, but I can't get it working. Get noise & distortion, guess the active divider isn't working.

I'm using 4*fs (non-oversampling application),
and BC557B's for the PNP's
The negative voltage is -6.1V
I measured -10V DC voltage on pins 16 & 17.

The FF indeed has the 4fs signal on it's outputs and there is some sawtooth on the DEM pins (noisy), but no luck.

Anyone ?
 

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It's in a cd player, so I do have the 11MHz.
As I menioned, the divider and FF work ok,
I have the 4*Fs square waves on the FF outputs.
In fact I have tried 8*Fs as well.
If you're interested I send you some scope shots of what I'm seeing.

The original DEM with capacitor:
Measuring a pin to ground shows a sawtooth; there is a phase difference between the two pins resulting in a triangular signal when measuring between the two pins of +/-0.5Vac @ -10Vdc

With the DEM reclock circuit:
Measuring a pin to ground shows something like a sawtooth; like the inverse of the signal that is shown in the picture. But there is a lot of "noise" like small oscillation superimposed that signal.
Also the AC value is at least halved.

I've also tried with 2.2k and 3.9k in stead of the 2.7k
With higher resistors, the ac value goes up in amplitude, but the sawtooth ramp rate stays the same, resulting in a bigger "step" when the other transistor is switches.
 
The DEM reclocking is working now :clown:
Was a problem unrelated to the circuit as supplied by Henk ten Pierick.

Im must admit, didn't expect a lot from it, but the improvements are not subtle at all.

Two things pop out:

First the clarity of voices and instruments, they sound clearer, easier to follow and differentiate.

Basses seemed less at first, but they sure were faster and much tighter. The TDA1541A imho always had a bit of woolly bass compared to other dacs, but not anymore.

Minor improvements:
Treble seems to have less roll-off
Agility factor improved, it's quicker in a positive way.


I've implemented the 4*FS DEM reclocking for a non-oversampling TDA1541A-S1. I've not implemented the BCK reclocking yet, as I wanted to do the mods seperately to hear their effects.

My next implementation will be a little different;
use the VHC series logic 74VHC74 without any need for inverters since my Kwak-Clock has inverted clock output as well.

I would say an improvement as big as installing a low jitter clock or getting rid of opamp I/V stage :att'n:

Cheers,
 
DEM mod very worthwhile

Hi All,

Finally got around to doing this DEM mod for the TDA1541 and yes, it is worthwhile. My observations are as follows:

1. Much better detail retrieval, especially stuff that was unresolved before.
2. A better sense of intimacy and musicalness in recordings
3. Notes have more separation and individuality.
4. Bass seems tighter, and again there seems to be more individuality to notes instead of the usual smearing.
5. Guitars, etc have more immediacy

The board (I have made several) also provides an option to reclock BCK.

This is in my heavily modded Rotel 955:
1. Zero-oversampling, i.e. SAA7220 bypassed
2. TDA1541 uses TL431 based power supplies
3. IV conversion as per rbroers "simple IV converter". He posted schematics here some time ago.
4. Seperate transformers and AC-DC for 1541, 7210 and processor
5. High speed diodes for rectifying
6. Ferrite beads and inductors (0.2 ohm DC) used in CDP
7. KWAK CLOCK v 6

Other things to do include:
1. Use of CMC coils in the power supplies
2. Optimising the TL431 based PS
3. Improving the IV converter to DC-coupled
4. Adding an output buffer along the lines of BUF04

My 2c.
Ryan
 
Hi All,

I'm trying to implement DEM reclocking as well. I have one question on the schematic which I hope the guys who have implemented the DEM reclocking successfully can share their thoughts on.

Is there any purpose to connecting pins 3 & 4 (D0 & D1 for ws_in) and pins 2 & 5 (Q0 &Q1 for ws_out) together? It would appear to me that ws_out is now a 10V clock whose voltage is double (due to the summation of Q0 & Q1) that of the normal ws clock. Wouldn't this have any adverse effect on the TDA1541A chip?

If there's really no purspose to the above, why not just use D0 for ws_in with its corresponding Q0 for ws_out only. For those thinking of reclocking BCK as well, just use D1 with its corresponding Q1 to do so.

I sent an email to Mr. Henk Ten Pierick but have yet to receive words from him. Anyway, I thought it may benefit all to have the discussion on DEM relocking here on the forum.

Best regards,
Moe
 
Hi All,

My implementation of the DEM relocking is finally working and it complement my tda1541-based non-os dac (which I also recently completed, I will post a new thread on my DAC soon :) ) very well. Mr Henk Ten Pierick has kindly replied me on the questions I raised in my previous post. below are his comments:

"The output signals at Q0 and Q1 are the same because their inputs are also connected together. The output voltage of Q0 and Q1 is the same, therefore the outputs can be connected to each other and is equal to the supply voltage of the latch. The parallel connection does not influence the output voltage but doubles the available output -current-, there is more drive current. This is beneficial because we want to drive the pnp transistors."

my implementation differs slighly from the original schematic - 1) I'm reclocking bck instead of ws. 2) the divided freq is derived from Q5 of 4024 (4*Fs) instead of Q4.

Right now, I just want to sit back and "rediscover" music. When I get around to doing some more mod, I intend to try out the following:

1) replace 74hc4024 with 74vhc4040 (dont think there's a vhc version of 4024) - to reduce propagation delay of divided freq.

2) replace 74hc04 with 74vhc04. reason as above.

3) replace 74hc174 with 74vhc374 and reclock all 3 lines (data, bck & ws) together with the required current drive for the pnp transistors.

4) try 8*Fs for non-os application?

Best regards,
Moe
 
PH2369??

Quick question... I am looking to implement this DEM reclocking circuit. The diagram at the start of this thread indicates a ph2369 transistor. This is an NPN transistor, not a PNP as indicated on the diagram.

Could someone confirm this, and suggest a suitable PNP to use?

Thanks!!
 
no. I haven't got the chance to do any comparison yet. Right now, I'm busy with my home renovation. I may do so when the reno is complete in the next 2-3 months.

I'm pretty much satisified with my 1541 implementation. however, i do notice that, from time to time, noise always creeps into the music. the noise is the hissing type that fluctuates with the music. changing orientation of the 3-prong plug, conntecting a piece of copper wire from the rca ground to the chassis and moving the interconnection cables seem to help eliminate the noise but sure enough the noise is again there after a few days, sometimes even lesser. I believe I have either a ground loop issue or my dac ground wasn't implemented correctly. If anyone has a solution to offer, bring it on! I will appreciate it very much. I intend to seriously look into this issue before I start on my second dac project (based on 1543 this time round) in the next few months.

Thanks!
 
:) DEM recloking working!

I have implemented this in my non os TDA1541 S2 dac (pictures will follow sometime....) along with reclocking of Fs, Bck and Data using a 74VHC373 as suggested by moemoe. I am using a Tent XO to generate a free running clock and using 74HC163 synchrous dividers to send Fs and 64Fs to the CS8412 receiver. As suggested by rudolf, generic PNPs were used for the DEM reclocking. Everything as usual P2P wired on perfboard.

Overall, the reclocking and DEM mod have made a substantial difference to overall sound quality. First was the I2S reclocking, then the DEM mod. Both mods take the sound in the same direction, if anything the DEM mod made more of a difference than the I2S reclock.

Subjective listening comments:

Positives:

1) Significantly improved dynamics and transient definition e.g. plucked guitar strings
2) Much tighter bass, drums have impact now e.g. those on the opening to Dire Straits 'Money for Nothing' rather than being flabby and loose
3) Cleaner highs, esp. female vocals. Norah Jones voice has taken on a whole new dimension!

Negatives:

1) Sound stage seems to have narrowed in both width and height, this may however simply be a result of instruments being locked better in space

I had compared my TDA1541 S2 dac (before I2S reclock & DEM mod) to a Doede Dac (multiple TDA1543) and although the S2 was preferred for capturing the texture and tonality of instruments, the Doede was much better in terms of dynamics and solidity of instruments, especially in the bass region. Now I would say the S2 is equal to the Doede in dynamics and bass but much better in capturing textures and atmospherics, also vocals much smoother.

These comments are all based on feeding both the XO and logic circuits with a non-optimised 317 regulator. When I get a moment I will put a proper power supply in, I'm leaning towards Jung reg for the clock and current sourced 431 shunt reg for the logic.
 
After some mails with Henk about why he reclocked WS, the conclusion is (with an I2S player, e.g. the 960):

Reclocking of BCK is most important (in and output latches are clocked on BCK) and reclocking WS and DATA is beneficial too.

Reclocking of the DEM clock before the transistors is done for removing jitter introduced with the 4024.

I'm going to implement it too, but i have to do two dac's :D, so it might take a while.

Greetings,
 
guido said:
After some mails with Henk about why he reclocked WS, the conclusion is (with an I2S player, e.g. the 960):

Reclocking of BCK is most important (in and output latches are clocked on BCK) and reclocking WS and DATA is beneficial too.

Reclocking of the DEM clock before the transistors is done for removing jitter introduced with the 4024.

I'm going to implement it too, but i have to do two dac's :D, so it might take a while.

Greetings,


Guido,


What is a latch? Is is the instant when the DAC reads the input data (or outputs the analog data)?

And can't reclocking one or 2 of the I2S lines cause problems, since there will be a delay between them?

Thanks
 
Now looking at the logic used.

A standard 4024 is slow, so you need to invert the clock of the '174. Otherwise the '174 would be clocking in and the 4024 hasn't clocked out yet....:dodgy:

delay of the 4024 is 50/60 nSec. 11.2896MHz is 88nSec, so 44nSec between clock high to low and low to high. With the
inverter you get 88nSec+inverter delay for the 4024 to output the data instead of 44nSec which is not enough.

So don't use a superfast 4024, say with a delaytime which matches the inverters delaytime. The 4024 would be clocking out while the '174 is clocking in...:hot: And the '174 needs some time that the data needs to be stable before clocking.

Faster logic isn't always better :whazzat:

Or if you use a superfast 4024 you could remove the inverter in the clockline of the '174. The 4024 then has 44nSec minus the '174 setuptime for dataoutput. :angel:

Fmax of a 4024 is typical 10MHz at 5V, that is less then 11.2896 :xeye: And minimal is only 5MHz :hot:
(looking at philips datasheet of standard CMOS HEF familiy).

Anyone looked at this? Which logic are you using?

Greetings,
 
Zodiac said:
Hi Guido,

Re the logic question...If you use syncronous dividers such as the 74HC163 then delay becomes much less of an issue compared to binary counters like the 4024 / 4040. I am using these without an inverter on the clock line to the flip flop.

Rgds.

Thanks,

You have confirmed my thoughts. I'm going to look what i can get easiest/cheapest on logic. Wanna try and find a FF with inverting output (like '74) so i can do without inverter all together. But maybe i'll put it together the way Henk did. As long as i understand what is going on :D mmm sortof :angel:

:clown: mvg