lossless overcurrent protection in UcD scheme

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I have simulated and also tested this circuit, and it seems to work. Do you have any opinions regarding the distortion from the added gate capacitance versus the distortion added by the regularly employed resistive current sensing elements?

The circuit below is to be used with a UcD style modulator, only the power stage and protection is shown here. On/Off is modulated by pulling the grounding of the CCS in the modulator differential pair.http://zilog.dyndns.org:8080/lagenheten/lossless_Ids.png

The current is sensed by voltage drop across the sensing mosfet. leading and trailing false readings are blanked (the mosfets switch simultaneously so I blank for both mosfet:s leading edges in the final measurement).
 
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Errrr, well. Don't get me wrong but at first glance it's a bit tricky to figure out what is going on and then it does not seem to do what I thought it might be doing.

It does initially look like what you are trying to do is implement something like the HexSense method provided by IR in a range of their mosfets whereby part of the main mosfet is re-connected to provide a sampled ratio of the overall current. You are adding the extra device plus resistance to do it (but I might be wrong).

Problem is that in order to get the right answer it is recommended that the sampled current sensed through the summing junction of an operational amplifier, if the sensing ratio is to be maintained. If you don't then you get errors. Unfortunately, in your case, you haven't got one of those.

Anyway, that was my first guess. As you have things set up all your additional (sense?) mosfet is doing is sampling the voltage across the main mosfet at the 'correct' time so you are using the RDSon of the main mosfet as your current sense resistor.

The rest of it is blanking and level shifting.

How about this one.......?

limbasic.gif

It still senses the voltage drop across the main mosfet using the Vbe of Q1 and Q3. However Q2 and Q4 are used with their resistors to, sort of, disable sensing when the associated mosfet is not active based on what the main output node is doing.

LIMH and LIML end up being ground referenced, with the diodes saving the day, but will need a little bit of processing. You can do the blanking downstairs as well.

Actually it looks a bit flakey to me, more thinking required. However it's not too different to what you have at the moment?

DNA
 
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zilog said:
Genomerics,

Why doesnt my circuit work as intended? Rds(on) of the mosfets increase with temperature, and allow for earlier tripping if the mosfets are too hot.

Perhaps I have misunderstood what I thought you were trying to achieve in the first place.

It's just that your description and the circuit looked like an attempt to do something similar to what IR's HexSense mosfets do.... However, looking at the circuit, it doesn't.

If you were not thinking of that in the first place, and you just wanted to use the main mosfet RDSon as a current sense resistor, then mine might do what yours does in a simpler way.

limaddeda.gif

Gets me down to ground and gives a preliminary 'Oh Sh1t' pulse

Maybe....

DNA
 
Hi Zilog

Here you have a commercial working implementation of your idea.
Is very efficient as far as I know…:up:
 

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TOINO said:
Like QSC PLX series power supply... they sense current on the resonant coil.
Same models sense also trough the LF output coil.
It is maybe not very precise but is enough for short circuit detection.:yes:

Exactly! Toino

In Class-D we usually talk about short circuit protection not a VI limiter........as in linear amps...

It seems to me that you are very active in posessing schematics of PRO AMPS....and also enjoying reading them too.....:D :D :D ;)

regards,
K a n w a r
 
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