High idle current on crown-BCA output? hjelp!

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http://users.rsise.anu.edu.au/~felix/iar/Projects/Thunderball/

I have made something similar along that schematic but output stage is hugging current. At 200v(or +-100) idle current is 500mA per bridge half, ie 200W IDLE full-bridge losses are toooo much. I have used large 500uH toroid inductors. N-mosfets are STW20NA50, 2 pieces parallei. gate resistors 4r7, 9Amp gate driver chips with isolation transformers.

And how do i calculate idle current in BCA output in ideal case?

Forgot, switching freq is lowish 100khz.
 
mzzj said:
Anyone? anything?

there is something really strange going on as i measured about 5A near constant dc current trough inductors in idle state. How is this possible? Goes over my understanding...

OK, i think i got it. Made some simulations and 1% unbalance in pulse width results several amperes dc current trough inductors. Pulse widht seem to be 50% as accurately i can see on scope, but its difficult to see it with 0.5% accuracy.

Offset in triangle generator or comparators i guess. Now i have to make offset adjustement to my modulator, never tought that problem is there.
 
alfsch said:
well, theres no dc feedback, so any offset will cause dc current flow...
maybe you should think about a feedback to correct it always..;)
Not sure what you mean but DC feedback doesnt help as this thing draws current even without load connected. And offsetting input voltage has no effect on quiescent current.

Problem solved anyways, I created adjustable offset for triangle waves. Funny thing though is that i need to adjust output stage for 43/57% duty cycle to minimize supply current. Something weird going on in output stage as so large duty cycle imbalace is is needed to minimize idle current.

BCA seem to have its own idle current issues...
 
Hi,

Hope you didn't copy the circuit exactly as presented in the link as there are 'issues' with that schematic. There is no proper dead-time controll. This could be what is causing your high current consumption. Operating at too low a frequency for your output filter can also cause high idle current. This is a carrier amp so if all is well and your final power stage is being driven cleanly you should have virtually no current consumed at idle regardless of offset ( presuming no load ), certaintly no more than around quarter of an amp just to drive the output fets gate. As usuall the bootstrap supply seems wrong. seems to be a common mistake with this i.c, people just keep bodging this part of the design. If you want my advice i would start by reducing the fet gate resisters to around 4.5R and then implementing an external dead-time circuit before the driver chip. Also check your filter and if possible get a scope on the fet gates to check for clean squares, also do the same for the bridge and sort out that bootstrap charge circuit.

Good luck.
Mad.P
 
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