IVX said:
I recommend that you try LTspice. It's free and in my opinion is faster, more powerful than Pspice (don't know about MicroCap) and easier to use. The link to the download is at the start of this thread (it is only a few megabytes).
By the way, it seems that THD as reported by the .four command is not reliable with these class D simulations. The numbers vary too much with the integration method, tolerance setting, maximum step size, total interval, etc. I can get either of the LeapFrog or the UcD design to come out with better THD by playing around with the simulator settings. Worse, there is no simulator control set up that consistently yields the lowest THD. The numerical noise is just too high to measure low THD reliably. That must wait for the actual hardware, it seems.
Regards -- analogspiceman
IVX said:Do you plan to build LF amp?
My modest DIY experience, in the real implementation of the class D amps, doesn't show even 50% THD matching vs simulations (MC7, P-spice), and i've feeling that it isn't only from the bad quality of the implementation/equipments etc.
I have no immediate plans to build an either of these designs although it might be fun to do a layout - and then, who knows?
Class D THD can be sensitive to layout imperfections via self EMI - bad layout may increase THD. Simulated Class D THD can be sensitive to computational imperfections - bad time step quantization may increase THD. So, in your experiences, which way did it go?
By the way, I am attaching the LTspice files for the two schematics shown earlier. (Remember, the first post in this thread has a link to where one may obtain a free copy of LTspice.)
Regards -- analogspiceman
analogspiceman said:
I don't know..i'm just a DIYer.
!!!Seems your amp will be well work without input+feedbacks_summing opamp. I just now check this out. Sure that opampless circuit much more preferable.
Maybe replacing ifb inverting opamp is possible also, with symmetrical mirrors instead? And all this come to the fully differential view (i'm saw it somewhere without ifb though..;-)?
Hi analogspiceman, I played with the UcD circuit to see how I could adjust its performance. I was wondering if you'd like to see what I came up with. I don't think it is as optimized as I could get it, but I thought I'd post the LTspice circuit how I got it after a while. I was wondering how it compares to the leapfrog method, in your opinion. I added rc passive damping to the output and adjusted the feedback.
Hi Subwo1,
I have not simulated yet, but I have a gut feeling that your added 10R resistor will have a rather high power dissipation.
Hi Analogspiceman,
thank you for posting simulation files. I agree with Subwo1, much food for thought.
I would also be interested in simulations using averaged models. So far I have modified some Ispice buck and boost stage averaged models to classD totem pole stage averaged model. But my model is only useful for constant frequency PWM. Bruno proposed method for devising UcD averaged model, but since it has been some years back when I played with Ispice models, I would have to relearn everything back.
Best regards,
Jaka Racman
I have not simulated yet, but I have a gut feeling that your added 10R resistor will have a rather high power dissipation.
Hi Analogspiceman,
thank you for posting simulation files. I agree with Subwo1, much food for thought.
I would also be interested in simulations using averaged models. So far I have modified some Ispice buck and boost stage averaged models to classD totem pole stage averaged model. But my model is only useful for constant frequency PWM. Bruno proposed method for devising UcD averaged model, but since it has been some years back when I played with Ispice models, I would have to relearn everything back.
Best regards,
Jaka Racman
Hi Jaka Racman,
I was wondering if you remembered that the 10R resistor in series with the capacitor raises the impedance to 27 ohms. Then, I come up with 11 watts. It is definitely not useful for high power applications. So the advantage of leapfrog for efficiency seems good. Thanks for taking a look at it. Best Regards.
I was wondering if you remembered that the 10R resistor in series with the capacitor raises the impedance to 27 ohms. Then, I come up with 11 watts. It is definitely not useful for high power applications. So the advantage of leapfrog for efficiency seems good. Thanks for taking a look at it. Best Regards.
Hi Jaka,Jaka Racman said:
Forgive me for retreading ground well known to you (I think it is always worth a revisit).Bruno's method seems sound in principle although he may have gotten some of the details wrong. The same method is used for analyzing digital gate driven low level, phase shift and crystal oscillators. There, as with UcD, there is a gross over abundance of gain until the output stage is limited by saturation. If everything is symmetrical then the output will become a square wave. Its fundamental Fourier component is in phase with an rms value of 0.9 times the dc supply (for plus and minus supplies). Follow the loop around through the RC phase shift network (or crystal, or UcD's LC filter) back to the input of the gate (or power stage) and sine wave that shows up is always precisely what is required for unity loop gain at the oscillation frequency. Saturation makes it self adjusting.
Ah, but stable oscillation requires more than just unity loop gain. It also require precisely 360 degrees of phase shift around the loop, and that only happens at one frequency determined by the feedback network and the gate or power stage delay. The UcD starts out with 180 degrees of phase shift because due to feeding everything back into the inverting input. Add the nearly 180 degrees from the LC filter and, whoops, we're in trouble because we are very close (but not quite at) the conditions for oscillation. Not good - lots of ringing and who knows what random extra bit of phase shift will put it over the edge and where it will oscillate.
Bruno's bit of genius
was to throw in a lead network (takes away 90 degrees of phase shift) to set the oscillation point at where the lead network runs out of steam. Of course, there still is the problem of only just barely reaching 360 degrees, but by this point, the delay in the power stage adds enough additional phase shift so that zero phase point (same as 360; it wraps! 
) is crossed with a well defined slope. This makes for a reliable and repeatable oscillation frequency. (Not enough delay can be remedied by adding a small RC section into the feedback path, most likely at the input to the power stage.)So, loop gain at the oscillation frequency is just the transfer function of the LC output filter plus feedback network, but what is it in the audio band? Just as with a typical sawtooth PWM modulator, one need only look at the slope of the wave form appearing at the input (a small sine wave) to the comparator / power stage and calculate how much change it would take along that projected slope to go from zero output to full output.
It turns out that it would take a change of 1/4 the period of oscillation to saturate the power stage along this slope. So if we know the frequency of oscillation and the size of the sine wave appearing at the power stage's input, we can calculate its slope at zero crossing (the point of switching). From this and the voltage of the power supplies and the gain factor of 1/4 the switching period, we can calculate the small signal gain within the audio band.
This is essentially Bruno's method, but I think he calculated a typical UcD design audio loop gain of over 400. When I work through the numbers for the UcD schematic I posted, I get a much lower number, somewhere just under 60. The devil's in the details, eh?
Regards -- analogspiceman
Howdy,
Good analysis.
Cheers,
Bruno
PS: More precise analysis shows that in this sort of phase-controlled circuit, loop gain at the switching frequency always ends at -6dB. The rest of the curve follows.
Good analysis.
There must have been a slight miscommunication somewhere. I was quite aware that loop gain is not 400. Numbers like that are not the loop gain, but the linearized gain of the comp+power stage alone. The loop gain is that multiplied by the "gain" of the filter and the feedback network. The standard 2nd order circuit from the patent (2nd order = only the output filter) typically clocks in at 25dB loop gain, the 3rd order circuit (1 extra passive pole) such as that used in the hypex modules has about 33dB loop gain (still less than 60). Not that I would mind 400analogspiceman said:
(...)
although he may have gotten some of the details wrong.
(...)
but I think he calculated a typical UcD design audio loop gain of over 400. When I work through the numbers for the UcD schematic I posted, I get a much lower number, somewhere just under 60. The devil's in the details, eh?
Cheers,
Bruno
PS: More precise analysis shows that in this sort of phase-controlled circuit, loop gain at the switching frequency always ends at -6dB. The rest of the curve follows.
Hi,
Subwo1, sorry I goofed but I did not have my old HP71B calculator at hand.
Analogspiceman, I was hoping to see more comments from other members. Right now, LF is very appealing to me since it can also work with fixed frequency control. Recently I discovered US patent 4479175 which has now expired. It renewed my interest in ampliverters. Since they work constant frequency, UcD control is out of the question.
I have three questions:
-do you think that for fixed frquency operation, average current mode loop could be used with equally good results as it is possible with hysteretic current mode control?
- what do you think about curent sense method that integrates output inductor voltage instead of using direct sensing? I know that inductor saturation could be problematic, but what else ?
-do you think that LF method could be improved by summing output of voltage error amplifier with differentiated input signal (capacitor current feedforward like in Mueta)
Best regards,
Jaka Racman
Subwo1, sorry I goofed but I did not have my old HP71B calculator at hand.
Analogspiceman, I was hoping to see more comments from other members. Right now, LF is very appealing to me since it can also work with fixed frequency control. Recently I discovered US patent 4479175 which has now expired. It renewed my interest in ampliverters. Since they work constant frequency, UcD control is out of the question.
I have three questions:
-do you think that for fixed frquency operation, average current mode loop could be used with equally good results as it is possible with hysteretic current mode control?
- what do you think about curent sense method that integrates output inductor voltage instead of using direct sensing? I know that inductor saturation could be problematic, but what else ?
-do you think that LF method could be improved by summing output of voltage error amplifier with differentiated input signal (capacitor current feedforward like in Mueta)
Best regards,
Jaka Racman
Bruno Putzeys said:There must have been a slight miscommunication somewhere. I was quite aware that loop gain is not 400. Numbers like that are not the loop gain, but the linearized gain of the comp+power stage alone. The loop gain is that multiplied by the "gain" of the filter and the feedback network. The standard 2nd order circuit from the patent (2nd order = only the output filter) typically clocks in at 25dB loop gain, the 3rd order circuit (1 extra passive pole) such as that used in the hypex modules has about 33dB loop gain (still less than 60). Not that I would mind 400
PS: More precise analysis shows that in this sort of phase-controlled circuit, loop gain at the switching frequency always ends at -6dB. The rest of the curve follows.
Hi Bruno,
Yes, I probably misread something somewhere, as I am getting my information about the UcD180 design all second hand from back threads, other posters and guesses. By the way, I went through the math regarding the two loop gains, and you are quite right, taken against each other everything drops out except a factor of two (at least at 50 percent duty cycle and as long as the signal appearing at the UcD input is more or less a sine wave).
Delays in the power stage (or right half plane zeros) eat your phase margin without giving back more loop gain, so a responsive power stage with a 3rd order type circuit would be best. Because this is a phase controlled, gain saturating oscillator, it might be difficult to get an even higher order, higher gain, marginally stable system to start up reliably oscillating at the right frequency. Oh, well.
Depending on what's driving it and how the inputs are configured, the UcD might need something (couple of diodes) to keep the input BE junction from Zenering. Also, with mosfets that need it (or to limit EMI), you might find my simple drain-to-gate RC dv/dt limiter useful, since the UcD is already set up perfectly with asymmetrical drive (its got the pull-down PNP that the RC needs so it only affects turn on dv/dt).
I'm very impressed with the UcD's elegant simplicity most of all. I like it (please tell Jan-Peter that if you get too busy with other projects, I'm ready to step in).
Jaka Racman said:
Hi Jaka,
A friend of mine actually made a working inverter using that phased carrier concept. It works fine, but can be difficult to snub simply. In the end, he decided it was more costly than traditional approaches.
Three Q's: 1) probably, but comparing theoretical bandwidth (after correcting for hysteresis control's wildly varying frequency) would be very interesting. 2) Risky. Loss of tracking during saturation could be a disaster and thermal resistance shift in the wire would be problematic. 3) ??? Leapfrog already feeds forward the output capacitor's load current. Did you mean something else?
To Subwo1,
Actually you stole a little bit of my thunder. I was going to mention the output damper as a possible addition to the UcD to cure its transient ringing, but Jaka already covered the down side of that. Note that with most loads, it wouldn't be a problem anyway and it might be better just to step around the "problem" by limiting the input signal appropriately (I know, some people don't like such circuits, but it is much easier to do it colorlessly on the low power input than on the high power output). By the way, from the power supply world, the standard recommended Q killing RC damper is 3*C and R = sqrt(L/C).
Regards -- analogspiceman
analogspiceman said:(please tell Jan-Peter that if you get too busy with other projects, I'm ready to step in).
I forgot to finish ... step in and design a LeapFrog version.
Forgot to mention ... a clever input limiter can also solve the problem of passing along power supply hum during clipping:
Actively peak track and low pass filter the lowest points of power supply ripple. Further reduce this by a signal proportional to mosfet current (compensates for IR drop). Scaled down just a bit, this then becomes a moving reference for an input limiter that always allows maximum possible output power (with no hum during "clipping"), and without ever having the output stage actually saturate and suffer the ill effects of opening the feedback loop.
Regards -- analogspiceman
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