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Class D Switching Power Amplifiers and Power D/A conversion

Help with class D university project
Help with class D university project
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Old 12th November 2019, 03:34 PM   #1
stwesty is offline stwesty
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Default Help with class D university project

Hi I am new here and have a university project to make a diy class D audio amp and the simulation deadline is very soon. I can't figure out why the design does not like having a negative voltage at the bottom n-mos, I thought it should pull the load voltage down. Can anyone see some stupid and obvious mistakes?
Screenshot 2019-11-12 at 15.31.31.pdf

fulldrivertester.asc
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Old 13th November 2019, 06:11 PM   #2
Mark Tillotson is offline Mark Tillotson
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You've pulled the gates to the sources with resistors - you don't do that with a gate driver chip, the chip wants a purely capacitive load for the top device gate so its bootstrapping can work. C2 is _horrendously_ large. The bootstrap cap should be about 10 to 20 times the gate capacitance normally. I think you were trying to compensate for the erroneous gate resistor.

Go study the IR2110 datasheet carefully for recommended circuits. You would be much better off using a gate driver that had programmable deadtime since you must prevent shoot-through, but you want to minimize deadtime too in class D.


The IR2110 has no shoot-through prevention at all, but you are giving it signals that will cause shoot-through. The MOSFETs explode if you do this. The simulator cannot tell you this except by the massive current spikes if you monitor the device currents.

Last edited by Mark Tillotson; 13th November 2019 at 06:14 PM.
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Old 15th November 2019, 05:31 PM   #3
nigelwright7557 is offline nigelwright7557  United Kingdom
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The gate resistors should be nearer 10r than 100r
You need a diode anode to gate and cathode to other side of gate resistor to give some dead time.
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Old 15th November 2019, 09:37 PM   #4
MorbidFractal is offline MorbidFractal
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10/10 for admitting to panic mode.

You should learn to drive the software to at least be able to draw pretty circuit diagrams.

I assume you know scientific notation.

What the others, who might now tumble in and slap me about, said plus...

Prior to ripping this off you might want to think about what I think I might have been thinking about. I am not knowingly right and you will look a bit silly if you cannot convincingly argue my case to your tutor.

You may wish to link to this thread in your thesis.

E&OE


...
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Old 18th November 2019, 05:35 PM   #5
stwesty is offline stwesty
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Quote:
Originally Posted by MorbidFractal View Post
10/10 for admitting to panic mode.

You should learn to drive the software to at least be able to draw pretty circuit diagrams.

I assume you know scientific notation.

What the others, who might now tumble in and slap me about, said plus...

Prior to ripping this off you might want to think about what I think I might have been thinking about. I am not knowingly right and you will look a bit silly if you cannot convincingly argue my case to your tutor.

You may wish to link to this thread in your thesis.

E&OE


...
Thank you so much for this it really helped understand where I was going wrong. I was wondering the need for Q1? Is it a buffer of some sort?
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Old 18th November 2019, 06:16 PM   #6
NMOS is offline NMOS  Germany
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its a long way starting from scratch,

it takes years of learning trial and fail for good design

DIY have working project, add what you need or remove what you dont need and finish university project

BE aware Class D have many big holes and you will go 100 % first times go in

study class D rules and design and select carefully componets, wrong mosfets give you a big nightmare
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Old 18th November 2019, 06:43 PM   #7
MorbidFractal is offline MorbidFractal
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Quote:
Originally Posted by stwesty View Post
Thank you so much for this it really helped understand where I was going wrong. I was wondering the need for Q1? Is it a buffer of some sort?

Level shift from the comparator, +2.5V/-2.5V, to the dead time logic and VLL, VDD, of the IR2110, +5V,0V.


Oh... A copy of the LTC6752 data sheet is included in the zip file. I'm not certain how the LTSpice model implements the actual device but VCC to VEE is 5V max and VDD to VEE is 3.15V max. You would tie VDD to ground in the circuit as drawn to avoid hurting it.

Last edited by MorbidFractal; 18th November 2019 at 07:01 PM.
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Old 20th November 2019, 04:55 PM   #8
Mark Tillotson is offline Mark Tillotson
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Quote:
Originally Posted by nigelwright7557 View Post
The gate resistors should be nearer 10r than 100r
You need a diode anode to gate and cathode to other side of gate resistor to give some dead time.

Faster switch off than switch on is not the same as deadtime. Its also going to increase distortion, crisp switching on both edges will minimize jitter. That means accurately generated deadtime should be used, such as a high-low gate driver of the right sort can provide. Switch off one MOSFET, delay by deadtime, switch on the other. The deadtime needs to allow for the slowest total switch-off time of the first device less the turn-on delay of the second device.



Too much deadtime will work but reduces performance as the body-diodes get in on the act and they aren't linear in behaviour and have lots of charge-storage (parallel schottky diodes can be added to improve this aspect).
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