|Class D Switching Power Amplifiers and Power D/A conversion|
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|3rd January 2018, 12:29 PM||#1|
Join Date: Nov 2016
Location: Shropshire, England UK
More RF than AF, but FET driver chip advice sought pleaase!!
Having received excellent help for my 136kHz projects here previously I hoped some of the experts might find time and inclination to read my problems modding a working Class D push pull RF amp for LF ham radio usage?
I have run a Class D push pull FET based PA on LF (137kHz) for a long time, with no issues. It's exciter is a cheap kit from QRP Labs called a U3S. The amp is from an American hams' design and has worked fine. In a can't leave well alone moment I decided that as the designer of the U3S exciter had issued a new firmware update for its Atmega 328 processor that allowed toggling the Si5351A synthesizer to output two 180 degree out of phase signals, from CLK0 and CLK1 pins, these could be used to delete an IC (Flip Flop 74F74 that divides by two and inverts signal) in the amp and to drive the FET driver IC directly.
Rather than spend an hour typing it all out I am taking the liberty of copy pasting what advice and questions I have received and posted on the UK LF forum, so you can see what's been tried. Basically I have changed from the IR2110 FET driver that needs 5V and 12V supplies to an MCP1404 driver IC that uses a single 12V supply, so also i lose a 5V voltage regulator too. I have it working (ran all night last night) but to do so I have to meticulously adjust the voltage to this driver IC to around 9V. Much less and the gate and drain waveforms of the PA FET's go to hell in a hand cart, and the same, but more so, with a near 12V supply.
Here's where we have gotten so far! Thanks for reading, it's a bit long winded...
I use my U3S QRP Labs exciter to drive a PA on 137kHz, and it works
fine. Hans, the designer, made changes allowing a 180 degree out of
phase pair of signals to come direct from the Si5351A synthesizer chip with
the intention of this being able to drive a push pull Class D FET
driver chip directly without a X2 signal being divided and split by a
preceding IC, please see original and simplified circuits below. I
tried this but it appears the circa 2.2V outputs of the Si5351A chip
are not sufficient to drive the inputs of the IR2110 FET driver.
Any ideas please? Thanks.
Original PA circuit (works fine with "normal" U3S driving the 74F74
direct with CLK0 output):
Modded amp circuit (simplified in the hope of building with one less
IR2110FET driver specs:
74F74 IC specs:
U3S exciter schematic:
Seems an odd choice of driver chip. A high/low side driver used in a non-bootstrapped mode to drive two low-side FETs
How about one of the normal FET driver chips - picking out one I've used in the past, the MCP14E 3/4/5 family. Logic level input, spec. Logic '0' max 1.3V, Logic '1' min 2.4V. So bias half way and your 2.2V swing takes it into the valid range.
They three types are inverting, non inverting, and one of each in a package
OK, this seems to continue the simplify quest rather than
transformers, plus I can delete the 5V regulator. I think I have some
MCP1404 driver chips, if I have I'll knock something together and report
back, thanks Andy.
MCP1404 IC fitted, as soon as power to the PA FETS is applied (even
6V) one of the gate square waves either disappears or becomes
extremely random. Swapping inputs to the driver IC makes no
difference, it's one pair of PA FET's dependent. FET's work fine when
returned to "as designed" status! Driving the driver IC through the
1nF caps and 15k resistors to ground. Outputs from CLK0 and CLK1 are
180 out of phase and seem correct. Any ideas please? Thank you!
So am I ok using another pair of 15K to pins 2 and 4 up to pins 6 (12V
DC +)? Thanks, this is all rather academic, given the latest U3S
firmware allows direct output of two signals from the Si synthesizer
180 degrees out of phase I just fancied seeing if I could reduce the
component count of an amp.
When I said bias half way, meant half way between the two logic threshold limits. Ie mid way between 1.3V (upper limit of guaranteed '0' and 2.4V (lower limit of guaranteed '1') so bias at 1.8V
Not half the supply volts.
Study the data sheets and calculate. Don't just play with components willy-nilly
Hello Andy, OK, understood, I did some calculations then checked them against an
on-line calculator and get figures of 68K and 12K for the divider. If I
retained the existing 15K to ground I might be able to use 82k as the
other half? Or are these values too high for needed current flow?
An "Online calculator" Whatever is that. Do you mean the basic equations for a potential divider?
Vout = Vin . (Rb / (Rt + Rb)
There is no leakage current into a CMOS input so those will do as well as any other pairings. Check the chip data sheet, it gives you all the values you need
Hello Markus / Andy / all,
Please see http://www.gatesgarth.com/amp-simplified3.jpg
I added 2 off 86k resistors as resistive dividers as shown. Voltages
were as expected 1.87 and 1.86V on pins 2 and 4 but both driver output
pins sat high at circa 12V . Removing the added resistors but running
the MCP1404 on 9V all works fine with gate and drain waveforms as
But on much less than 9v, say here at 6.8V the waveforms deteriorate and output is noisy:
and with the supply at near 12v things totally fall apart with the traces rapidly degenerating into hash around 11.7V :
Not sure why this is so....Have I misunderstood the bias at 1.8V Andy
suggested?? By e-mail from Andy:
"When I said bias half way, meant half way between the two logic
threshold limits. Ie mid way between 1.3V (upper limit of guaranteed
'0' and 2.4V (lower limit of guaranteed '1') so bias at 1.8V
Not half the supply volts.
Study the data sheets and calculate. Don't just play with components
Thanks. Any /all pointers to what is happening welcome!
I am wondering if the input capacitance of the two pairs of FQA34N20L FET's (worst case 7800pF, best case of 6000pF for a pair) is pushing this driver which is rated to deliver into 5600pF in 34nS
If I used a pair of TC4452 driver IC's (each 8 pin device has only one input and output) these are capable of supplying 22,000pF in 42nS so have a lot more oomph. Am I looking in the right direction or way off track please??
|3rd January 2018, 03:39 PM||#2|
Join Date: Jun 2004
1. Why AC couple ( and 'bias', wrongly) logic signals from clock chip to mosfet driver input?
2. knock, knock, who's there, not DEAD TIME for sure
3. The 'twisted pair' whatever it is gives me some uneasy feelings. FWIW my experience is the wires (if any) between fet driver and fet gates must be very short. none is best. 15cm of twisted fet gate drive wires gave me headaches at 16kHz switching some time ago, compact PCBs is the way.
4. what is the RF transformer construction? spread inductance?
5. On the modified circuit - why was pin11 (assume VDD) left unconnected?
6. TC44xx idea is good - much better suited for the job.
Last edited by darkfenriz; 3rd January 2018 at 04:05 PM.
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