Class D amp with 300v mosfets

...had a closer look to the data sheet of the driver.
It has a nice strong output: In terms of current capability it might
work to drive the SiC Fets directly with 6R8 for turn on and shottky+2R2 for turn off - but I guess thermal stress will be to high (did not calculate..).
Simply step into the equations of the data sheet and you will see if the driver will run hot or not.

Did your recommendation takes into account Rg=7 ohms of sct3030al? Because I not included in my calculus, means the temperature rise is much lower.
 
My proposal are the values for the external resistors. For the heat calculation you have to add the Rg inside the Sic Fet.
...promising, the impedances inside the driver are low, so already without
external PNP most of the gate charge related losses are moved outside the driver towards the external resistors and gate resistance inside the SiC Fet.
Such a tiny chip...., but able to drive the fat SiCs without much external support, did not expect that. But usually such calculation results of the losses of the gate driver are fitting to reality. No hidden obstacles to be expected there.
You should also calculate how much heat you will get in the external resistors.
 
This is some documentation about IGBT and SiC related to solar inverters:
- CREE guy showing 50kW solar inverter prototype 2 years ago:
YouTube
I feel at CREE they are working with funds not from previous work but from aids, and trying to aesthetically clean up switching without enough experience on which imperfections matter more, so that a 50kW inverter can be made 100khz, with single stage boosting, and straight hard switched 2 switch per phase output stage, like a 500W inverter.
- Various Infineon brochures discussing several options:
https://www.infineon.com/export/sit...promopages/mc_events/pcim2014/pdf/Solar_1.pdf
https://www.infineon.com/cms/cn/pro...discretes_for_solar_inverter_Vincent_Zeng.pdf
https://www.infineon.com/dgdl/Infin...N.pdf?fileId=db3a30433e5a5024013e6a33393f6360
I feel the ones not blindly promoting SiC have deeper experience. Infineon papers show 3-level inverters for minimization of switching loss, facts like 50kW range is lowest sales, clever combination of Si FET, SiC FET/diode and IGBT, etc. (and even SiC diodes at the output of a LLC where a Si diode is lower loss, just for marketing, with modest fooling pretensions).

And both companies still have to discover switching optimizations down to physical limits, variable-frequency "constant ripple" modulators, capacitors across switching transistors, resonant topologies, semi-resonant topologies with helper switch/network, etc. CREE also has to discover 3 level modulation, good for big inverters with slower switches and lower precision demand.

Do you figure out the problem now? Some of us, audio designers, are the actual owners of the key knowledge for making optimum solar inverters in all senses, and application-optimized semiconductors.
 
Do you figure out the problem now? Some of us, audio designers, are the actual owners of the key knowledge for making optimum solar inverters in all senses, and application-optimized semiconductors.

That is a forked tongue statement.

Solar inverters success (apart from the obvious that you mentioned) is the power tracking algorithm, and the new ones are moving into the machine learning space where data science will make far more predicative analysis offline inside the firmware as appose to hill climbing and perturbation detection algorithms.
 
That is a forked tongue statement.

Solar inverters success (apart from the obvious that you mentioned) is the power tracking algorithm, and the new ones are moving into the machine learning space where data science will make far more predicative analysis offline inside the firmware as appose to hill climbing and perturbation detection algorithms.

Sorry ionutgaga for offtopic discussion, but this is somewhat the other side of the subject.

MPPT is solved with a self oscillating loop. Just flip sign of constant V source feeding duty cycle integrator after a certain time of negative slope on power output.

Sun can be tracked with panel orientation servos using a similar algorithm, only executed for a few oscillations every few dozen minutes or hour, for longer servo life.

Funny point Choco.
 
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Remember fast (<1us latency) over-current shutdown. Otherwise each mistake can cost 50 euro plus shipping! In these situations one learns to love IRS20957 and its current limiting adapting to junction temperature and allowing to use full transistor capabilities, but is there a higher voltage version of gate driver IC with integrated sensing across Vds/Vce? Otherwise there are little Vds/Vce sensing ICs like IR25750.

btw: Full carrier removal is cosmetic, Italians did it that way, then others copied. I care more about clean 20hz-20khz output.
 
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- Td-on is 385ns typ. Tdoff is 340ns typ. Slow chip. I got fast with IR2110 and opto.
- The current limiting of both channels is hardwired together regardless of BTL. There is a single CSD line. If ch.1 has a bad load, ch.2 does not produce sound. This is not good for 2ch rack amplifier, unless both channel are BTL.
- I suppose external comparator is tolerated by driving COMP pins with logic signal.
- PWM may not be mandatory, but there is no explanation of PWM mechanism.
- Pricing seems adequate.

In the end this is a magnified LF boombox chip. The high propagation delay prevents good amplifier performance at high frequencies. Imagine Behringer or the Chinese relasing an ultra-long excursion subwoofer with ultra high power amplifier, and using this chip and some 600V IGBTs or 300V FET. And maybe non-isolated PSU with speacial speaker driver.
 
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Hello all, is the confusion about strange ROHM -4V abs max rating already solved?
I am trying to simulate a self oscillating class D full bridge using 350V bus voltage and SCT3030, UCC21521C plus bootstrapping hi supply.
I am trying to get some negative gate "for free" by zener diode plus cap in series to gate, maybe -1.5V at the gate, but dependent on duty cycle and no negative voltage at startup. Not sure if the -4V is a mandatory limit. But anyway, I think the ROHMS are good at ~-1V and plus 16 ... 19V (depending on load current).
(I built a simulation using LTSPICE incl. the models of driver and SIC, but no chance to get the simulator to show anything. Just convergence issues, "time step too small", def con... etc...)
 
Hello all, is the confusion about strange ROHM -4V abs max rating already solved?
I am trying to simulate a self oscillating class D full bridge using 350V bus voltage and SCT3030, UCC21521C plus bootstrapping hi supply.
I am trying to get some negative gate "for free" by zener diode plus cap in series to gate, maybe -1.5V at the gate, but dependent on duty cycle and no negative voltage at startup. Not sure if the -4V is a mandatory limit. But anyway, I think the ROHMS are good at ~-1V and plus 16 ... 19V (depending on load current).

In my application and as per ROHM technical team suggestion, unipolar gate drive serves the purpose. They are recommending +18V/0V gate drive. Which I have also found to be adequate. In case if you want to have negative gate drive, it should not increase beyond -4V at any cost, otherwise traps will form in the die and impact the reliability.


Whereas the real issue with CREE and ROHM SIC is as follows:

1. The Rthjc junction to case is very high when compared to other same package mosfets/Igbts. For example Rohm SCT3060AL specifies Rthjc as 0.91C/W vs 0.27C/W of IXGH100N30C3 IGBT.

This severely hampers the operation at high frequencies >250khz at higher currents >25A.

As per CREE and ROHM, they are Trench SIC mosfets whose DIE area is smaller as compared to other mosfets and hence higher Rthjc and higher RDS ON [compared with equivalent VCES drop of IGBT]

Hence the Fmax2 limit suffers severely, even if you have lower Total switching loss.

2. The Body Diode drop is very high 3-4V, which means you have high voltage drop during third quadrant switching or during deadtime. To keep this low, one has to keep the deadtime low or have to use external high voltage schottky barrier diode to keep the dissipation at minimum by bypassing the internal body diode voltage drop, though RDS based current path shunting does help but not much.. Again this conduction loss of diode increases the case temperature and further creates reliability problems.


IMHO these SIC mosfets are more suitable for use at high rail voltages , low current and lower frequencies.:D

See the attached graph based on data provided by ROHM itself.
 

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@Workhorse:
I am not so sure if SiC Fets really have a bright future.
IMHO the next 5 years will show if GaN Fets turn more affordable and their formerly issue with dynamic Rdson really is solved, if yes - they have good chances to wipe out SiC Fets.
...or some other fancy wide band gap stuff suddenly turns hip for switches...

What you have to say now in the case of SIC ??

I guess times have changed, SIC is the present as of now :wave2:
 

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