For example:
Given: N-Channel MOSFET
VGS = 10V
t (transistion) = 25nsec
Find: Gate drive current, IG.
From the MOSFET manufacturer’s specifications, QG = 50nC at
VGS = 10V. Using IG = QG/t(transition):
IG = QG/t(transition) = 50 x 10-9/25 x 10-9 = 2.0A
I would not recommend using IRFP250 for class D designs , if you like me and don't have money (and being a newbie) for expensive switching output mosfets, I would recommend using an IRF540Z as the lowest possible price, most suitable transistor...
IRFP250 are old, and just looking at a few critical parameters;
Total Gate Charge = 120nC vs IRF540Z 63nC
Rds = 0.085Ω vs IRF540Z 0.0265Ω
DSv = 200v
so i have this output stage built, but i have a massive dc offset at the output, about -15V. what am i doing wrong here???
An externally hosted image should be here but it was not working when we last tested it.
COM is connected to ground ?? COM (return) PIN be connected to -VCC.
VB High side floating supply absolute voltage VS + 10 VS + 20
VS High side floating supply offset voltage Note 1 200
VHO High side floating output voltage VS VB
VCC Low side fixed supply voltage 10 20
VLO Low side output voltage 0 VCC
VIN Logic input voltage (HIN & LIN) COM 5.5
Also note you wired up the IC by the looks of it with reference to the data sheet example that doesnt use a +/- supply but a + and ground.
please spend some quality time with the datasheet.
http://www.irf.com/product-info/datasheets/data/ir2011.pdf
VB High side floating supply absolute voltage VS + 10 VS + 20
VS High side floating supply offset voltage Note 1 200
VHO High side floating output voltage VS VB
VCC Low side fixed supply voltage 10 20
VLO Low side output voltage 0 VCC
VIN Logic input voltage (HIN & LIN) COM 5.5
Also note you wired up the IC by the looks of it with reference to the data sheet example that doesnt use a +/- supply but a + and ground.
please spend some quality time with the datasheet.
http://www.irf.com/product-info/datasheets/data/ir2011.pdf
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that makes a lot of sense thank you. also the datasheet for the ir2011 says the logic input should ideally be 0V to 5.5V, but my pwm square wave currently goes from +-5V. should i level shift it to 0-5V?
Hey all, I'm working on this project with jmp and we ran into an issue. Based on your suggestions we ended up changing the voltage of the rails to +/- 15 so we could use ground for Vcc, in order to satisfy it needing to me 12-15 volts above the negative rail. Without a load we have what we want in the output (no dc offset) but once a load is introduced there is a -13v offset on the ground rail. Our ground is isolated from the power supply ground with a coupling capacitor, we measured this as the potential before and after the coupling capacitor. I'm absolutely confused as to how this is happening and makes me think there is an issue with our implementation, I'm guessing trying to use ground for Vcc? Any thoughts?
When I remove the capacitor I get an overload on the -15v voltage rail, it pulls down the voltage to around 9 and tries to put an amp through. The positive rail is fine. My guess is that this may be caused from the relationship of Vb and Vs? I'm not sure if I'm understanding the datasheet correctly, right now still have Vb tied to Vcc (ground) but looking at the datasheet I don't think this should be the case, should Vb instead be tied to the positive voltage rail?
The more we help you, the more we start to understand how lazy you are the answers you seek is right under your nose, here is some tips.
The MGD (mosfet gate driver) has so many thread entries that cover this very topic, it almost feels wrong to help you cause by doing so will only allow the manifestation of lazyness and block conscious reasoning.
Read some technical literature on bootstrapping using IR MGD drivers ICS there is one good paper that covers this in detail (look through their classd papers) you then understand what each pin does during switching operations.
Alright so after a long day of reading and tweaking our design we have an open loop circuit running at the moment and the sound is surprisingly clear without the feedback loop. Basically what we did was tie both the FETs and the gate driver to the same power supply at -7 volts and +8 volts. This was due the fact that we were having issues when we tied two PSU's together.
We have COM/lowside FET at -7 volts and Vcc/highside FET at 8 volts. This put us at 15 volts above the negative rail but not quite Vb = Vs +10 (though I still don't think I am understanding that correctly). I'm in the process of drawing up a full schematic of our circuit to give the details of the rest of the changes which contains our previous stage as well.
I did notice that the lowside FET was getting warm to the touch. We are still testing on the circuit to see if this increases with time. We're still a little uneasy leaving the circuit on for an extended period of time after a long day of working on it, thinking we might have missed something.
I just wanted to thank everyone for the help so far as well as Reactance for the suggested reading!
We have COM/lowside FET at -7 volts and Vcc/highside FET at 8 volts. This put us at 15 volts above the negative rail but not quite Vb = Vs +10 (though I still don't think I am understanding that correctly). I'm in the process of drawing up a full schematic of our circuit to give the details of the rest of the changes which contains our previous stage as well.
I did notice that the lowside FET was getting warm to the touch. We are still testing on the circuit to see if this increases with time. We're still a little uneasy leaving the circuit on for an extended period of time after a long day of working on it, thinking we might have missed something.
I just wanted to thank everyone for the help so far as well as Reactance for the suggested reading!
You didn't specify what type of mosfets you are using.. note i would recommend using +/- 25v as the lowest supply voltage im pretty sure the gate turn on threshold needs approx 12v for proper reliable ton/toff operation.
The mosfets we are using are the IRFB4019's. We believe we may have blown the IR2011 gate driver late last night while trying to implement the feedback loop. None of our replacements seemed to fix the problem but the FET's tested good. We were forced to switch to the IR2010 gate driver that we have a few extra of and managed to get sound through though it's not as clear as our IR2011 design. We are also getting a much higher sourced current from the PSU (200mA vs the 50mA we were getting from the 2011) and the lowside FET heats up. I'm reading and rereading about each stage to try and find where we went wrong but figured I would give an update as to where we were at. I'll keep you guys posted.
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