i tried some of the design posted in this forum but aint make no good.....ended up with burning a huge stock of mosfets with no succes....signals are shown on the gate point before connecting mosfets and they disppear after connecting them.....and if worked then it would be for a while....can any one suggest in a simple manner why the hell this happens...
warm regards
warm regards
they tend to oscillate easily. You need to keep very short lead lengths. Have decoupling cap at the fet - not at the power supply. And a gate resistor of a few hundrd Ohms close to the gate lead. These are the typical things to do to prevent oscillations which destroy the fet. if you have a 100Mhz scope, you could see possible oscillation at full power happen.
Other common problem is misidentifying the leads - which is gate, drain and source. double - triple check.
Other common problem is misidentifying the leads - which is gate, drain and source. double - triple check.
An interesting point when playing fet's, is NEVER, NEVER, NEVER let the gate pin floating
. Always define a level for it. As it is capacitively coupled with the main current channel, though this capacitance, the gate left open circuit may capture some charge from main channel, opening it randomly, and creating a DC path trough it. As the FET has both current and voltage from drain to source, is becomes class A (linear region) biased, and may be destroyed if this point is outside the SOA of the unit. This can happen in few milliseconds. For avoid this situation, use a 100K resistor between gate and source, when there exist possibility to the gate bias to be removed
.
This sometime happens in SMPS manipulated by unexperienced people.
Good luck!.
. Always define a level for it. As it is capacitively coupled with the main current channel, though this capacitance, the gate left open circuit may capture some charge from main channel, opening it randomly, and creating a DC path trough it. As the FET has both current and voltage from drain to source, is becomes class A (linear region) biased, and may be destroyed if this point is outside the SOA of the unit. This can happen in few milliseconds. For avoid this situation, use a 100K resistor between gate and source, when there exist possibility to the gate bias to be removed.This sometime happens in SMPS manipulated by unexperienced people.
Good luck!.
it would be easier to everyone to help with your problem if you could attach as much pictures as possible. pictures of your pcb, pictures of your mosfet, ir2110, soldering and the signal trace at some important point.
the best post that i've came across explaining how to troubleshoot a class d design is as below:
the best post that i've came across explaining how to troubleshoot a class d design is as below:
people are building the irs900d problem free. so the pcb works. you then decide to start your class d journey with a new, unconfirmed pcb that nobody have given any feedback for. it's better to start with a simpler design and work from there.
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