Im trying to optimize a diamond buffer module for my preamp. In doing so ive come to ponder if its a good idea to keep the power traces on bottom layer and then all signal traces on top layer, which is the opposite of the advice ive read in the past.
My thinking is that if the power traces are on the bottom then shieled by a top layer ground plane then top becomes the layer with the lesser radiated interference and thats where the signal traces should go. Please let me know if thats a sound plan
My thinking is that if the power traces are on the bottom then shieled by a top layer ground plane then top becomes the layer with the lesser radiated interference and thats where the signal traces should go. Please let me know if thats a sound plan
Depends. If you're minimizing inductance, you'll want the traces on the top layer as that minimizes the lead length for the parts. If you're trying to minimize the coupling between the supply traces and other traces, you really could go either way.
That said, I doubt coupling between the supply traces and the other traces in the diamond buffer would be the limiting factor. I bet the PSRR of the circuit and the cleanliness of the supply would be the limiting factor for supply noice.
There's a certain temptation to put all the traces on the top layer and have a solid ground plane on the bottom. That would give you the lowest ground impedance, which could possibly be of benefit.
If you're curious about the layout's impact, you can always simulate it. You can figure out the capacitance between traces from the relative dielectric constant of the PCB material and its thickness along with the area of the intersecting copper. If you run the traces super tight together, you may have to account for the fringe cap in places.
PCB inductance can be modelled as 1 nH per mm of trace.
Obviously an EM field solver would be even better, but above will get you close enough to see if there's anything to worry about.
Tom
That said, I doubt coupling between the supply traces and the other traces in the diamond buffer would be the limiting factor. I bet the PSRR of the circuit and the cleanliness of the supply would be the limiting factor for supply noice.
There's a certain temptation to put all the traces on the top layer and have a solid ground plane on the bottom. That would give you the lowest ground impedance, which could possibly be of benefit.
If you're curious about the layout's impact, you can always simulate it. You can figure out the capacitance between traces from the relative dielectric constant of the PCB material and its thickness along with the area of the intersecting copper. If you run the traces super tight together, you may have to account for the fringe cap in places.
PCB inductance can be modelled as 1 nH per mm of trace.
Obviously an EM field solver would be even better, but above will get you close enough to see if there's anything to worry about.
Tom
If your power and ground traces come from a well regulate power supply then you will not induce noise from the PS into the signal lines. In any case, the more distant you can put between any two traces the lower interaction from inductive and capacitive coupling. Listen to tomchr, good info there.