You used to be able to purchase such sockets with the cap already mounted. Not sure they still exist.
Jan
How do you take into account the effect of board parasitics on your loop gain and phase plots?
A loop gain/phase plot gives you essentially the same information about stability as a small-signal step response, it is just somewhat more complicated to simulate and much more complicated to measure. Then again, it gives you information about how effective the feedback is that you can't get from a small-signal step response. Do whatever you like best.
A loop gain/phase plot gives you essentially the same information about stability as a small-signal step response, it is just somewhat more complicated to simulate and much more complicated to measure. Then again, it gives you information about how effective the feedback is that you can't get from a small-signal step response. Do whatever you like best.
Hi, Marcel,
You can measure the board parasitics, or you can estimate them from the physical dimensions of the PCB. Trace thickness, width, and length determine L & R. Distance determines mutual L coupling Trace spacing and PCB layer thickness determine C. It's really a lot of work.
High-end PCB layout software can calculate those parasitics for you, and add them to your SPICE netlist. For high speed digital and RF design, these values are critical. For audio, they don't really matter, so long as some basic layout rules are followed: Keep traces on op-amp inputs short. Don't run large signals next to small, high-impedance ones. Keep outputs away from inputs. Loops with high AC current should be kept small, because a large inductance is formed by the loop area.
Bypass caps satisfy the last rule. High supply resistance and inductance can cause oscillation by magnifying the AC current of the IC. Initial bypass should be as close as possible to make the loop, and thus the L, small. On the IC at the output transistors is 1st. (That's for the IC designer to do, ha!) Then 0.1 uF ceramic on the IC pins. I like SMD caps for this because of lower lead inductance and ability to put them closer to the IC. Then a heftier bypass to GND not too far away. Then bulk caps somewhere on the PCB. The idea is to keep reducing the magnitude of the AC current the farther you get from the IC.
Before I started doing high-speed ADC design, I designed IC buck converters and class D amplifiers for a living. Five years ago, I designed an IC buck converter switching at 100+ MHz. First, I interleaved the buck-converter power transistors with bypass caps (on the chip), then put in larger bulk Cbypass on the chip, then 0.1uF in SMD off chip, tied to a GND plane that was an entire layer of the PCB, and 100uF bulk cap at the power terminals. di/dt is reduced by each step of decoupling to a level that lets you tolerate the parasitics of the next larger loop. IC layout parasitics, bond-wire or ball parasitics, PCB trace parasitics, then bulk C to smooth supply ripple.
You can measure the board parasitics, or you can estimate them from the physical dimensions of the PCB. Trace thickness, width, and length determine L & R. Distance determines mutual L coupling Trace spacing and PCB layer thickness determine C. It's really a lot of work.
High-end PCB layout software can calculate those parasitics for you, and add them to your SPICE netlist. For high speed digital and RF design, these values are critical. For audio, they don't really matter, so long as some basic layout rules are followed: Keep traces on op-amp inputs short. Don't run large signals next to small, high-impedance ones. Keep outputs away from inputs. Loops with high AC current should be kept small, because a large inductance is formed by the loop area.
Bypass caps satisfy the last rule. High supply resistance and inductance can cause oscillation by magnifying the AC current of the IC. Initial bypass should be as close as possible to make the loop, and thus the L, small. On the IC at the output transistors is 1st. (That's for the IC designer to do, ha!) Then 0.1 uF ceramic on the IC pins. I like SMD caps for this because of lower lead inductance and ability to put them closer to the IC. Then a heftier bypass to GND not too far away. Then bulk caps somewhere on the PCB. The idea is to keep reducing the magnitude of the AC current the farther you get from the IC.
Before I started doing high-speed ADC design, I designed IC buck converters and class D amplifiers for a living. Five years ago, I designed an IC buck converter switching at 100+ MHz. First, I interleaved the buck-converter power transistors with bypass caps (on the chip), then put in larger bulk Cbypass on the chip, then 0.1uF in SMD off chip, tied to a GND plane that was an entire layer of the PCB, and 100uF bulk cap at the power terminals. di/dt is reduced by each step of decoupling to a level that lets you tolerate the parasitics of the next larger loop. IC layout parasitics, bond-wire or ball parasitics, PCB trace parasitics, then bulk C to smooth supply ripple.
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I estimate the lead wire parasitics of power transistors and include those in my simulation models of discrete class B amps. (Actually Bob Cordell estimated them, and I'm using his estimates. They seemed correct based on other bond-wire parasitic modeling I've done.)
I don't really bother doing this for the input or gain stages, because those currents are essentially constant, and with no di/dt, lead wire inductances make little difference.
I don't really bother doing this for the input or gain stages, because those currents are essentially constant, and with no di/dt, lead wire inductances make little difference.
I know, I design RF integrated circuits for a living. The point I tried to make in post #62 is that Bonsai's remarks about board parasitics in post #60 apply equally to his loop gain simulations.
Wire parasitics in input and gain stages can easily lead to parasitic oscillations, usually around the fT of the transistor, and usually solvable with base stopper resistors.
They still do exist, but they assume the standard digital IC pinout with supplies at the northeast and southwest corners. Many analog ICs have their supply pins elsewhere.
I don’t think it’s as simple as that.
The loop gain/phase plot is done ‘in loop’. If you close the loop at a reasonable frequency, you aren’t going to see anything at pico-second rise times.
1-2 pF stray capacitance in a 2-3 pico-second rise time is a big deal. 1-2 pF on an loop BW of 1-2 MHZ assuming no high impedance are involved is not.
Square wave testing is a key tool for evaluating stability (and the behavior of amplifier front end linearity for example), but I just don’t see how rise/fall times corresponding to GHz BW are relevant in the context of audio.
Anyway, each to his own.
^This
Re: LM4562 / LME49720 popcorn noise... I have a jig running as I write this, where 10 are 'baked' at once. The thing is, the noise often takes a few minutes (or hours sometimes...) to come on. When it does come on late, it tends to be spectacular, making the noise floor on the FFT look like a trampoline.
I've come to regard the 4562 as a much more expensive part than it is raw. Someone has to be paid to vet them. In quantity, a part that costs about $1USD has a real cost of 3 or 4. That's a reality I'm currently resigned to.
I haven't tried the 2134 in the circuit described here. I've always regarded it as a peach WRT stability. I must have been using it for maybe 15 years. I don't use it that often these days, though.
"Re: LM4562 / LME49720 popcorn noise....the noise often takes a few minutes (or hours sometimes...) to come on. When it does come on late, it tends to be spectacular, making the noise floor on the FFT look like a trampoline."
How far down of a noise floor are we talking here? Is this at -100 dbV or at -50, or......?
How far down of a noise floor are we talking here? Is this at -100 dbV or at -50, or......?
Making a video is on my to-do list. It won't make good watching for TI.
The 'trampoline' effect tends to be seen in the worst culprits. It typically lurks below -100dBV. I may have observed it at higher levels (I have several tubes of 'rogue' ICs). I've definitely never seen it above -90dBV, and cannot really recall if I've seen it above -100. The problem for me is that once I've seen it, I totally lose faith in the DUT. I don't feel comfortable giving it to a client, whether they can hear it (unlikely) or not. If you quote a particular spec, then you ought to meet it.
Some of the 4562 have a permanent noise trace, and some have the 'trampoline' effect. Off top of head, I'd say there are about 3 different manifestations of popcorn / burst noise. Around 30-40% of the ICs I test have it.
If I didn't have to solder the LME49860 into an adaptor, I'd use it in a flash. Regardless of what it costs us to vet the 4562s, particularly at present, we have low staffing levels - and having someone tied up staring at a screen vetting ICs is a preposterous way to use their time.
The 'trampoline' effect tends to be seen in the worst culprits. It typically lurks below -100dBV. I may have observed it at higher levels (I have several tubes of 'rogue' ICs). I've definitely never seen it above -90dBV, and cannot really recall if I've seen it above -100. The problem for me is that once I've seen it, I totally lose faith in the DUT. I don't feel comfortable giving it to a client, whether they can hear it (unlikely) or not. If you quote a particular spec, then you ought to meet it.
Some of the 4562 have a permanent noise trace, and some have the 'trampoline' effect. Off top of head, I'd say there are about 3 different manifestations of popcorn / burst noise. Around 30-40% of the ICs I test have it.
If I didn't have to solder the LME49860 into an adaptor, I'd use it in a flash. Regardless of what it costs us to vet the 4562s, particularly at present, we have low staffing levels - and having someone tied up staring at a screen vetting ICs is a preposterous way to use their time.
My experience with the 2134 is that it doesn't like being used as a unity gain buffer. It is perfectly happy as a unity gain inverter (like in tone control circuits). I also used it in a non-inverting gain stage with a voltage gain of 1.4 with no problems.
I have successfully configured it as a unity gain buffer with a few extra parts (couple of resistors and ceramic capacitors).
I built a prototype of this circuit Project 99 - Subsonic Filter with op amp sockets. I tested three op amps in the circuit: NE5532, LM4562, and OPA2134.
NE5532 worked great but DC offset was 45 mV.
LM4562 worked great and DC offset was 3 mV
OPA2134 oscillated. I tried using one 2134 and one 4562 and it oscillated.
To me, the 4562 should be the touchiest, with its 50 mHz GBP. But it seems that's not the case.
I have configured the 5532 as a follower with 0.1 to 0.2 mV DC offset, but obviously this isn't doable in a whole lot of circuits.
So has anyone else had a similar experience? I'm always looking for new tricks.
Dou you know the high speed layout guidelines ?
https://www.ti.com/jp/lit/an/sloa046/sloa046.pdf
GND management is also important.
Please upload an image of your PCB design (solder site) so as the wiring diagram to your power supplies.
Thanks for the link. Yes I read it a long time ago.
This is a prototype. It's built on this. https://www.mouser.com/ProductDetail/854-SB404/ It's powered from 9 volt batteries for testing, in series with a 10 ohm current sense resistor. It's not the final product. There are boards available and I'll take a second look.
I understand about layout and component placement. Resistors go close to the op amp. Capacitors can be antennas if not carefully placed. Long leads directly to the op amp are a no no. All traces are isolated by a series resistor.
My "fix" that I described is just a phase correction circuit. I read about it many decades ago in one of Walt Jung's many books. So this clearly points to a deficiency in my methods.
I do make PC boards. My methods are primitive and basically the same as I did in the 70s. I use stencils and enamel and an acid bath agitated by hand. I do make two sided boards and I do use ground planes.
This is a prototype. It's built on this. https://www.mouser.com/ProductDetail/854-SB404/ It's powered from 9 volt batteries for testing, in series with a 10 ohm current sense resistor. It's not the final product. There are boards available and I'll take a second look.
I understand about layout and component placement. Resistors go close to the op amp. Capacitors can be antennas if not carefully placed. Long leads directly to the op amp are a no no. All traces are isolated by a series resistor.
My "fix" that I described is just a phase correction circuit. I read about it many decades ago in one of Walt Jung's many books. So this clearly points to a deficiency in my methods.
I do make PC boards. My methods are primitive and basically the same as I did in the 70s. I use stencils and enamel and an acid bath agitated by hand. I do make two sided boards and I do use ground planes.
That's the "fix" I explained a page or two back.
The problem is that there is no feedback resistor. The inverting input and the output are directly connected.
It's not clear to me whether adding a feedback resistor (which would also reduce offset) would change the transfer function of this circuit.
The problem is that there is no feedback resistor. The inverting input and the output are directly connected.
It's not clear to me whether adding a feedback resistor (which would also reduce offset) would change the transfer function of this circuit.
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