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OPA2134 Stability
OPA2134 Stability
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Old 26th February 2021, 05:55 PM   #61
jan.didden is offline jan.didden  Europe
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Quote:
Originally Posted by dotneck335 View Post
You used to be able to purchase such sockets with the cap already mounted. Not sure they still exist.

Jan
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Old 26th February 2021, 05:57 PM   #62
MarcelvdG is offline MarcelvdG  Netherlands
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How do you take into account the effect of board parasitics on your loop gain and phase plots?

A loop gain/phase plot gives you essentially the same information about stability as a small-signal step response, it is just somewhat more complicated to simulate and much more complicated to measure. Then again, it gives you information about how effective the feedback is that you can't get from a small-signal step response. Do whatever you like best.
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Old 26th February 2021, 07:06 PM   #63
RussellKinder is offline RussellKinder  United States
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Hi, Marcel,
You can measure the board parasitics, or you can estimate them from the physical dimensions of the PCB. Trace thickness, width, and length determine L & R. Distance determines mutual L coupling Trace spacing and PCB layer thickness determine C. It's really a lot of work.

High-end PCB layout software can calculate those parasitics for you, and add them to your SPICE netlist. For high speed digital and RF design, these values are critical. For audio, they don't really matter, so long as some basic layout rules are followed: Keep traces on op-amp inputs short. Don't run large signals next to small, high-impedance ones. Keep outputs away from inputs. Loops with high AC current should be kept small, because a large inductance is formed by the loop area.

Bypass caps satisfy the last rule. High supply resistance and inductance can cause oscillation by magnifying the AC current of the IC. Initial bypass should be as close as possible to make the loop, and thus the L, small. On the IC at the output transistors is 1st. (That's for the IC designer to do, ha!) Then 0.1 uF ceramic on the IC pins. I like SMD caps for this because of lower lead inductance and ability to put them closer to the IC. Then a heftier bypass to GND not too far away. Then bulk caps somewhere on the PCB. The idea is to keep reducing the magnitude of the AC current the farther you get from the IC.

Before I started doing high-speed ADC design, I designed IC buck converters and class D amplifiers for a living. Five years ago, I designed an IC buck converter switching at 100+ MHz. First, I interleaved the buck-converter power transistors with bypass caps (on the chip), then put in larger bulk Cbypass on the chip, then 0.1uF in SMD off chip, tied to a GND plane that was an entire layer of the PCB, and 100uF bulk cap at the power terminals. di/dt is reduced by each step of decoupling to a level that lets you tolerate the parasitics of the next larger loop. IC layout parasitics, bond-wire or ball parasitics, PCB trace parasitics, then bulk C to smooth supply ripple.
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Last edited by RussellKinder; 26th February 2021 at 07:08 PM. Reason: grammar
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Old 26th February 2021, 07:14 PM   #64
RussellKinder is offline RussellKinder  United States
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I estimate the lead wire parasitics of power transistors and include those in my simulation models of discrete class B amps. (Actually Bob Cordell estimated them, and I'm using his estimates. They seemed correct based on other bond-wire parasitic modeling I've done.)

I don't really bother doing this for the input or gain stages, because those currents are essentially constant, and with no di/dt, lead wire inductances make little difference.
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Old 26th February 2021, 07:21 PM   #65
MarcelvdG is offline MarcelvdG  Netherlands
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Originally Posted by RussellKinder View Post
Hi, Marcel,
You can measure the board parasitics, or you can estimate them from the physical dimensions of the PCB. Trace thickness, width, and length determine L & R. Distance determines mutual L coupling Trace spacing and PCB layer thickness determine C.
I know, I design RF integrated circuits for a living. The point I tried to make in post #62 is that Bonsai's remarks about board parasitics in post #60 apply equally to his loop gain simulations.
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Old 26th February 2021, 07:24 PM   #66
MarcelvdG is offline MarcelvdG  Netherlands
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Originally Posted by RussellKinder View Post
I don't really bother doing this for the input or gain stages, because those currents are essentially constant, and with no di/dt, lead wire inductances make little difference.
Wire parasitics in input and gain stages can easily lead to parasitic oscillations, usually around the fT of the transistor, and usually solvable with base stopper resistors.
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Old 26th February 2021, 07:45 PM   #67
Mark Johnson is offline Mark Johnson  United States
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OPA2134 Stability
Quote:
Originally Posted by jan.didden View Post
You used to be able to purchase such sockets with the cap already mounted. Not sure they still exist.
They still do exist, but they assume the standard digital IC pinout with supplies at the northeast and southwest corners. Many analog ICs have their supply pins elsewhere.
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Old 26th February 2021, 08:02 PM   #68
jan.didden is offline jan.didden  Europe
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Probably geared to logic chips then. I think the 74xxx had supplies at opposite corners, 7 and 14.

Jan
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Old 26th February 2021, 08:07 PM   #69
bucks bunny is offline bucks bunny  Germany
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jan, you should switch to top view
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Old 26th February 2021, 08:41 PM   #70
Bonsai is online now Bonsai  Europe
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OPA2134 Stability
Quote:
Originally Posted by MarcelvdG View Post
How do you take into account the effect of board parasitics on your loop gain and phase plots?

A loop gain/phase plot gives you essentially the same information about stability as a small-signal step response, it is just somewhat more complicated to simulate and much more complicated to measure. Then again, it gives you information about how effective the feedback is that you can't get from a small-signal step response. Do whatever you like best.
I don’t think it’s as simple as that.

The loop gain/phase plot is done ‘in loop’. If you close the loop at a reasonable frequency, you aren’t going to see anything at pico-second rise times.

1-2 pF stray capacitance in a 2-3 pico-second rise time is a big deal. 1-2 pF on an loop BW of 1-2 MHZ assuming no high impedance are involved is not.

Square wave testing is a key tool for evaluating stability (and the behavior of amplifier front end linearity for example), but I just don’t see how rise/fall times corresponding to GHz BW are relevant in the context of audio.

Anyway, each to his own.
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