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Ultra low drift GAIN
Ultra low drift GAIN
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Old 16th August 2020, 01:45 PM   #71
mchambin is online now mchambin  France
diyAudio Member
Join Date: Mar 2011
Referring to posts #44 and 45.
Indeed, Phythagora is welcomed.
To see the effect of the open loop gain on the loop gain, I can write for a non inverting stage with resistors to set the gain g0
g0/g = 1 + g0/G
g is the actual closed loop gain
g0 the expected closed loop gain
G the open loop gain.
This is valid at DC.
This is valid too, at any frequency considering G is a complex number one could derive from the gain, phase plots from the datasheet.
At DC no problem, G is typically over 120dB, so with g0 =8 we have g/g0 better than 8ppm
At hight frequencies, it is not so fine because G is much lower. Assuming GB 10 MHz, at 20 KHz we only have G = 500 which gives
g/g0= 1 - 0.016, so terrible 16 000ppm.
Here comes Phythagorus, telling this result is wrong.
Indeed, G is not a real number, this gain has typically a phase -90.
This is consistent with post #44 and confirmed with post #45 where a plot shows phase -90 over frequencies from 100 Hz to 100KHz.
So at 20KHz, actually g/g0 = 1 + j 0.016
from Pythagora this gives 128ppm a totally different story.
All the above is about gain flatness.
To adress gain drift, all the above results have to be multiplied by the accuracy of G
Considering G has TC 0.1%/℃
Gain drift at 20KHz becomes 1ppm /℃
Transistor junction temperature is not transistor case temperature.

Last edited by mchambin; 16th August 2020 at 01:50 PM. Reason: I was wrong
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