Vendetta Research SCP-2A

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The Total Idss for a given combination of fets should be about 15-17 ma. It is of course, easiest to just use a single device with a 16ma Idss, like I do, but they are hard to get.
The second stage can be between 7-16ma. However, the key to getting a working design is to make sure that the dc supply resistor(s) are the right value. This is found by totaling the Idss of both stages and selecting a resistor that will keep the second stage device at about 1/2 Idss. This can be 'cut and try' until you get a good solution.
What I did was select the Idss's of both the input and second stage, then select a proper resistance that fed both of them properly. As I did it in batches, one calculation did a whole run of boards, but each of you MUST select the proper resistance so that the 2'nd stage runs in Class A mode. This is why I normally avoid this input circuit for most designs outside my personal attention, like AI or Parasound. Get it wrong, and it won't work. What you can do is start with a slightly higher resistance, like 500 ohm, then parallel a resistor, one on both sides, until you get lowest distortion at 1V or more.
 
The Total Idss for a given combination of fets should be about 15-17 ma. It is of course, easiest to just use a single device with a 16ma Idss, like I do, but they are hard to get.
The second stage can be between 7-16ma. However, the key to getting a working design is to make sure that the dc supply resistor(s) are the right value. This is found by totaling the Idss of both stages and selecting a resistor that will keep the second stage device at about 1/2 Idss. This can be 'cut and try' until you get a good solution.
What I did was select the Idss's of both the input and second stage, then select a proper resistance that fed both of them properly. As I did it in batches, one calculation did a whole run of boards, but each of you MUST select the proper resistance so that the 2'nd stage runs in Class A mode. This is why I normally avoid this input circuit for most designs outside my personal attention, like AI or Parasound. Get it wrong, and it won't work. What you can do is start with a slightly higher resistance, like 500 ohm, then parallel a resistor, one on both sides, until you get lowest distortion at 1V or more.
Thank you very much. I have perfectly matched K170/J74 Gr grade with Idss values of about 5ma. Is it possible to use four in parallel at the input?
 
The Total Idss for a given combination of fets should be about 15-17 ma. It is of course, easiest to just use a single device with a 16ma Idss, like I do, but they are hard to get.
The second stage can be between 7-16ma. However, the key to getting a working design is to make sure that the dc supply resistor(s) are the right value. This is found by totaling the Idss of both stages and selecting a resistor that will keep the second stage device at about 1/2 Idss. This can be 'cut and try' until you get a good solution.
What I did was select the Idss's of both the input and second stage, then select a proper resistance that fed both of them properly. As I did it in batches, one calculation did a whole run of boards, but each of you MUST select the proper resistance so that the 2'nd stage runs in Class A mode. This is why I normally avoid this input circuit for most designs outside my personal attention, like AI or Parasound. Get it wrong, and it won't work. What you can do is start with a slightly higher resistance, like 500 ohm, then parallel a resistor, one on both sides, until you get lowest distortion at 1V or more.
I have never seen Vendetta with single 2SK147 at the input. Does it mean two singles in parallel with 16-17ma each, or 8.5ma?
 
You are right, Kamis. I stand corrected, but my calculations remain the same, just more total Idss, perhaps 24ma on the input stage (with 10 ohm biasing) and then another 10ma for the second stage is optimum. Less will still work, but require a higher value load or feed resistor, maybe even more than 500 ohms, but I can't compute it without knowing what to work with.
 
Yes, Idss=16.3mA for ONE device ( Grade V ).
About 20V Supply, remember that is simulation only.
I built first stage according to Mr. Curl suggestions.. Everything measures well. I trimmed offset to zero and it is stable even without servo op-amp. I am planning to use OP27 which is 22V device. Original PCB layout is very cleverly designed. All J-fets are genuine and perfectly matched.
 
I built first stage according to Mr. Curl suggestions.. Everything measures well. I trimmed offset to zero and it is stable even without servo op-amp. I am planning to use OP27 which is 22V device. Original PCB layout is very cleverly designed. All J-fets are genuine and perfectly matched.

How do you trimmed to zero?

Regarding first stage, in my simulations ( with servo ) , the pot between the sources control 2nd and 3rd harmonics ratio , besides controls the current , due mismatch transconductance between N and P channel fets.
 
How do you trimmed to zero?

Regarding first stage, in my simulations ( with servo ) , the pot between the sources control 2nd and 3rd harmonics ratio , besides controls the current , due mismatch transconductance between N and P channel fets.
Turning 20Ohm trimming pot changes offset at the output and it is easy to trim to zero. It is not its role? You have been posting Vendetta schematics for years. Have you built it?
 
For purpose to learn more about how to get this circuit working with available jefts, I did this simulation with very good results.


Input Jfets: Idss = 16.3mA

Power Supply: 6 parallel Jfets per rail ( plus 1 Jfet for current source )

C1 and R15 values were modified for better FFT presentation.

C134 and C135 used for my own tests. They don´t belong to original topology.

Dear ED,
would you please share the ltspece file and required parts lib?

Thanks
Leo
 
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