LDR Pre MkII - LDR volume control and I/O switching

Just a Galaxy u3 with a Milled front panel
 

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Hi, ZDR,

You have done a great job with the LDR project! There is something that bothers me that you may be able to answer.

The LDR driver circuit has a MOSFET with a 220K gate-bleed resistor and a 20K trimmer resistor to the bias signal. At maximum trim value, the gate will be at (1 - 20/220) x 5V = 4.55V. That voltage should bias the FDV301N MOSFET on all the time, but no one has reported trouble with the circuit. What am I missing?

I appreciate your taking time to set me straight!

Sincerely,
- Guido
 
I ignored the 1K resistors in the gate filter? When there is no PWM signal, the input is pulled to ground so the gate has 220K in parallel with 2K, or 1.98K to ground. The 20K trimmer in series with the 2K-ish bleed resistor gives a minimum of about 0.45V at the gate, and can be increased with the trimmer. I think that is right.