I don't know enough about op-amps to skin this cat, so I was looking for ideas that might help from the gang.
The following circuit has a bad 781 kHz oscillation on the second stage of the chip. The first stage is oscillation free and clean.
The circuit is as follows:
I have also tried removing resistors R116 and R117. I also tried that and shorting R118 to make a traditional inverted op-amp buffer.
However the second stage still oscillates and I do not know why.
The chip is bypassed by ceramic .1 uF caps (C111 & C112), which are jammed as close to the supply pins as I can physically get them.
The layout may be the cause, but I am just guessing. Board size is 2.5" high by .9" wide, so it is small. Here are the three layers. The ground plane is a single plane with the only external ground connection at the top of the board going to a star ground. The other two "ground" connections are part of a twisted pair that simply terminates as a dead end wire on the input and output to prevent ground loops.
The power plane is split so that it supplies + and - 15 VDC supply. C15 & C16 are 10 uF. C17, C18, C19, & C20 are by-pass caps (.1 uF and .01 uF for each rail).
The wing shaped polygons are connections to two 100K pots. This board sits just behind the pots.
The following circuit has a bad 781 kHz oscillation on the second stage of the chip. The first stage is oscillation free and clean.
The circuit is as follows:
An externally hosted image should be here but it was not working when we last tested it.
I have also tried removing resistors R116 and R117. I also tried that and shorting R118 to make a traditional inverted op-amp buffer.
However the second stage still oscillates and I do not know why.
The chip is bypassed by ceramic .1 uF caps (C111 & C112), which are jammed as close to the supply pins as I can physically get them.
The layout may be the cause, but I am just guessing. Board size is 2.5" high by .9" wide, so it is small. Here are the three layers. The ground plane is a single plane with the only external ground connection at the top of the board going to a star ground. The other two "ground" connections are part of a twisted pair that simply terminates as a dead end wire on the input and output to prevent ground loops.
The power plane is split so that it supplies + and - 15 VDC supply. C15 & C16 are 10 uF. C17, C18, C19, & C20 are by-pass caps (.1 uF and .01 uF for each rail).
The wing shaped polygons are connections to two 100K pots. This board sits just behind the pots.
An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
According to Texas Instruments the OPA134 family is unity gain stable.
Then the next question is, what is wrong with the layout?
Is stage two really unity gain?
Stage one is, but that does not oscillate. Stage two has the tone network as part of the feedback loop and that can't be unity gain.
The oscillation is pretty high (781 kHz or a 180° phase shift of 500 nS). There would be some phase shift from the caps, but not enough to produce positive feedback, correct?
How do I test if this is a phase shift induced oscillation?
And how do I fix it if it is?
Well, what do you know?
A 20 pF ceramic SMT cap soldered between the two legs killed it.
Can you help me understand why?
Thanks!
The cap reduces the gain at HF. You can experiment and come down on that value. Even as little as a 3.3 or 4.7 pf may be enough.
R118 on your circuit isn't needed and can be shorted out. The FET inputs draw zero bias current but the inclusion of a resistor increases the impedance of that pin and makes it prone to stray pickup. That might be related to the problem too.
A couple of related threads here,
http://www.diyaudio.com/forums/anal...u-have-checked-see-its-stable-havent-you.html
http://www.diyaudio.com/forums/analog-line-level/196461-different-opamp-compensation-technique.html
R118 on your circuit isn't needed and can be shorted out. The FET inputs draw zero bias current but the inclusion of a resistor increases the impedance of that pin and makes it prone to stray pickup. That might be related to the problem too.
A couple of related threads here,
http://www.diyaudio.com/forums/anal...u-have-checked-see-its-stable-havent-you.html
http://www.diyaudio.com/forums/analog-line-level/196461-different-opamp-compensation-technique.html
Not with a FET opamp
There are no input bias currents (and hence no input offset voltage due to bias current) with FET opamps.
If it were a bipolar opamp like the NE5532 then the input currents should be matched to minimise DC offset.
Not with a FET opamp
There are no input bias currents (and hence no input offset voltage due to bias current) with FET opamps.
If it were a bipolar opamp like the NE5532 then the input currents should be matched to minimise DC offset.
Changing to 0.0 Ohms.
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