Reducing jitter on AES3 or S/PDIF is usually a very good idea. This can be done several ways.
If we stick to the PLL method for this discussion, the WM8805 does this with a built in fractional-N PLL method and gets to about a 50ps result. One of the advantages with this part is when you want to keep retransmitting in a long chain. You can grab the data and then retransmit to the next device.
I am not sure if there is another S/PDIF receiver that does this well. The WM8805 is now End-of-Life (EOL) from Cirrus.
Does anyone know of a good replacement for this technique?
Al
If we stick to the PLL method for this discussion, the WM8805 does this with a built in fractional-N PLL method and gets to about a 50ps result. One of the advantages with this part is when you want to keep retransmitting in a long chain. You can grab the data and then retransmit to the next device.
I am not sure if there is another S/PDIF receiver that does this well. The WM8805 is now End-of-Life (EOL) from Cirrus.
Does anyone know of a good replacement for this technique?
Al
Check with Rochester Electronics. They currently stock thousands of EOL Cirrus chips. The WM8805 is not in their catalog now, but it may be added.
In the data sheet it says the 50ps number refers to "intrinsic jitter." That is jitter added by WM8805 if the incoming SPDIF stream had zero jitter. Also, datasheet says for optimum performance a jitter-free crystal clock is required as a reference for the PLL. Turns out jitter-free crystal clocks don't exist, but SOA ultra-low phase noise clocks are available.
Thus, it doesn't seem too surprising the part is being discontinued.
WM8804!? Or is that one also obsolete?
Markw4, the part performs better than many a competitors product. Suppose you have an SPDIF only source: what receiver would you choose!? OP clearly explained the benefits of WM8805 in the specific situation of which retransmitting apparently is key parameter.
Edit: WM8804/5 can be ordered till september 1st 2024. Danville you can stock up in numbers and be the owner of a sought after chip.
Markw4, the part performs better than many a competitors product. Suppose you have an SPDIF only source: what receiver would you choose!? OP clearly explained the benefits of WM8805 in the specific situation of which retransmitting apparently is key parameter.
Edit: WM8804/5 can be ordered till september 1st 2024. Danville you can stock up in numbers and be the owner of a sought after chip.
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Don't know. Just saying "intrinsic jitter" is not total output jitter. Also saying a good crystal reference is required. Otherwise actual output jitter may be worse than expected. Not saying it doesn't sound good.
If using a good crystal reference then maybe it could be used to reclock the SPDIF output of a lesser SPDIF transmitter, thus potentially making jitter lower than 50ps?
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It does not matter as OP does not need to change a thing till september 1st 2024. The receiver better does not add more jitter than the source already provided does it!? And the retransmitting thingie makes choice difficult.
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The PLL attenuates incoming jitter by some unspecified amount. The output jitter should be the attenuated input jitter plus the intrinsic jitter. This of course assumes a jitter-free crystal reference. Otherwise PLL performance will be reduced.
Unfortunately WM8804/5 seems to be so far the only SPDIF interface chip that employs a fractional-N DPLL for clock recovery, and a SPDIF transmitter block supplied with that recovered clock. Others recover the clock with an analog PLL. Due to the PLL loop filter frequency response, it usually has no effective jitter reduction at frequencies under 1KHz, and some attenuation, perhaps up to 20db, at higher frequencies. However even such limited jitter attenuation property becomes irrelevant when it comes to the SPDIF output part, as majority of the SPDIF interface chips do not even have a "proper" transmitter block that operates on a jitter-attenuated clock for its SPDIF output. They just buffer and loop back the SPDIF feed they receive, passing the incoming jitter on down the chain, if not making it worse.
If we expand this conversation a little, lets assume that we would like to create a remote MCLK that is already recovered via extraction but has large jitter. This does not necessarily mean S/PDIF/AES3. There are many situations where digital redistribution will create this situation.
The jitter I am talking about might be in ns or large ps, not fentosecs, so the affect will not be subtle.
The WM8804/5 managed about 50ps which is not horrible in comparison to the input it was starting with.
I know you can still get WM8804/5 parts, but this is not a long term solution.
I think one step of solution would achieve clock recovery in a similar range to the WM8805. For example a Skyworks Si5351C might be reasonable, available and not particularly expensive. The Cirrus Logic CS2100 is another candidate. There are other PLL-VCXO type solutions that could be considered.
Another class of solutions would aim for better results - in the ps or fs region. One thing to remember is that the low frequency jitter matters.
There are many jitter attenuator chips designed for high speed networks. They are also fairly large and expensive In our case, we are likely looking at 24.576MHz or maybe 49.152MHz clock recovery .
So any ideas?
Al
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The jitter I am talking about might be in ns or large ps, not fentosecs, so the affect will not be subtle.
The WM8804/5 managed about 50ps which is not horrible in comparison to the input it was starting with.
I know you can still get WM8804/5 parts, but this is not a long term solution.
I think one step of solution would achieve clock recovery in a similar range to the WM8805. For example a Skyworks Si5351C might be reasonable, available and not particularly expensive. The Cirrus Logic CS2100 is another candidate. There are other PLL-VCXO type solutions that could be considered.
Another class of solutions would aim for better results - in the ps or fs region. One thing to remember is that the low frequency jitter matters.
There are many jitter attenuator chips designed for high speed networks. They are also fairly large and expensive In our case, we are likely looking at 24.576MHz or maybe 49.152MHz clock recovery .
So any ideas?
Al
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SPDIF itself is not a long term solution either.
A good DAC inside a source so without the need for any external digital interface really is best. It also saves trouble, time, and effort while giving a lot in return.
A good DAC inside a source so without the need for any external digital interface really is best. It also saves trouble, time, and effort while giving a lot in return.
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Most seem to now drop SPDIF and TOSLINK (to my dismay) and go USB-only. There is some validity to that approach.
Tom
The PLL acts as a lowpass filter for the reference clock and as a highpass filter for its local oscillator. If the local oscillator is low noise and the PLL loop bandwidth is set somewhat intelligently you get a low noise clock on the output.
Tom
I agree that S/PDIF is in decline, which is probably why the WM8805 is going away.
I make lots of boards that have local DACs and ADCs. On these boards, I work on making sure clocks are good.
Regardless, there are still many situations where MCLK recovery will be important. I mentioned the CS2100. It is also EOL, but replacements are in development.. I don't know anything about the new parts (CS2500, CS2501, CS2600). These are just referenced with information on the Cirrus website
Al
Interestingly the links to those replacement parts on Cirrus' website are all dead. A search for CS2500, etc. turns up nothing. Great work Circus Logic!
Another reason for EOL'ing the WM8805 could be that Cirrus has a similar IC: CS8416.
Tom
Another reason for EOL'ing the WM8805 could be that Cirrus has a similar IC: CS8416.
Tom
My source is SPDIF so I am also still using it. Hating it since it was invented but also loving it at the same time 😀
Tom, CS8416 is worse than WM8804/5. It is older too. My guess is that even todays cheapo LC89091 is better (no retransmitting though).
Tom, CS8416 is worse than WM8804/5. It is older too. My guess is that even todays cheapo LC89091 is better (no retransmitting though).
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True. In the case of an ESS dac chip there is a DPLL_Bandwidth register setting that can be adjusted to optimize PLL performance depending on incoming jitter. Do any of the SPDIF receivers allow user adjustment of PLL loop bandwidth?