Hi all,
I'm currently finishing a DAC design based on the PCM1794 without oversampling (DDDAC inspired), however, wonder which clock signal is normally the jitter - sensitive signal in a DAC ...
There's the master clock (MCLK), left/right shift clock (LRCK), bit clock (BCLK) and Data clock (DATA), however, which one of these defines when the output samples? To put it in another way: which clock input should be least affected by "anything" so as to make for the least jitter affected output sampling?
If one/more of you know I'd appreciate your input 😉
Jesper
I'm currently finishing a DAC design based on the PCM1794 without oversampling (DDDAC inspired), however, wonder which clock signal is normally the jitter - sensitive signal in a DAC ...
There's the master clock (MCLK), left/right shift clock (LRCK), bit clock (BCLK) and Data clock (DATA), however, which one of these defines when the output samples? To put it in another way: which clock input should be least affected by "anything" so as to make for the least jitter affected output sampling?
If one/more of you know I'd appreciate your input 😉
Jesper
Its different for different kinds of DACs - multibit ones depend on the BCLK. With this one my money would be on it being the MCLK which needs to be low jitter.
Hi abraxalito,
Thanks for your feedback ... Actually, in this particular design case it makes things easier as in the DDDAC both the MCLK & the BCLK are connected together (to omit the oversampling).
Cheers ;-)
Jesper
Thanks for your feedback ... Actually, in this particular design case it makes things easier as in the DDDAC both the MCLK & the BCLK are connected together (to omit the oversampling).
Cheers ;-)
Jesper
Hi,
Back on this post 🙂
Well in the NOS 1794 dac, BCK and SCK are wired, this is a trick from the author, so the low phase noise clock should either be sync with BCK or LRCK.
but normally the SCK is 4x BCK (or more). so the question remains : in a normal I2S setup, what is the signal which is more critical for PCM1792 or PCM1794 in regards to jitter or the trigger which transfer the data latch register to the analog part...
at the moment, there is an indication from Herbert Rutgers that SCK is to be the reference and that the PCM1792 would have its own reclocking mechanism internal.
anyone having done some test to confirm this ? Thanks
Back on this post 🙂
Well in the NOS 1794 dac, BCK and SCK are wired, this is a trick from the author, so the low phase noise clock should either be sync with BCK or LRCK.
but normally the SCK is 4x BCK (or more). so the question remains : in a normal I2S setup, what is the signal which is more critical for PCM1792 or PCM1794 in regards to jitter or the trigger which transfer the data latch register to the analog part...
at the moment, there is an indication from Herbert Rutgers that SCK is to be the reference and that the PCM1792 would have its own reclocking mechanism internal.
anyone having done some test to confirm this ? Thanks
I'm fairly certain that BCLK is the jitter sensitive clock signal for the PCM1794A. I've seen digital o-scope screen capture photos which clearly show the 1794A's analog output being updated exactly synchronous with each low-to-high transition of BLCK. This indicates that the device's 6-bit quantizer's output is clocked by BLCK, at 64x the input sample's native rate (prior to internal oversampling). It's only the timing of the analog output update instants that matter for jitter.
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My take on the DS leads to the opposite conclusion from you Ken - that its SCK which should be low jitter. Page13 talks about SCK needing to be low jitter - when talking about BCK there's no mention of jitter. Also they say SCK is what feeds the modulators, whereas BCK is mentioned in the context of loading the input data into shift registers.
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Richard, you are probably correct. I think there's no doubt that the SDMs are being run by SCK, so the 64Fs output update rate I saw on those screen shots was probably derived by dividing down SCK, and so, would show as synchronous with BCLK without being derived from it.
hi
i used to think all clock lines should be synchronized (as in page 15) and everything should be derived from master clock at the very best
so maybe Ken's observation just a coincident that BCK just happen to follow MCK?
i used to think all clock lines should be synchronized (as in page 15) and everything should be derived from master clock at the very best
so maybe Ken's observation just a coincident that BCK just happen to follow MCK?
ok seems we beleive here that SCK is the important clock and then the crystal should be close to it and used as the master for the front end side as well...
the only way to check this would be to drive 2 PCM with one having bck (or lrck) delayed by a couple of hc04 and then look at the 2 dac output... such experiment needs a pcb. also questioning this when used in DF mode...
the only way to check this would be to drive 2 PCM with one having bck (or lrck) delayed by a couple of hc04 and then look at the 2 dac output... such experiment needs a pcb. also questioning this when used in DF mode...
just bought this item
PCM1794A Adaptor | eBay
and a couple of 4040 an hc04 to make some real experiment.
my plan is to connect a 12Mhz crystal on 4040 then take BCK (Q2) and LRCLK (Q8) and a fake I2S data by using the Q12 (/4096). Hopefully I will get a 3 khz square wave at the output of the PCM (to be loaded by a 100ohms).
I will plug the oscope and see how things are synchronized, then I will put 4 gates HC04 to create about 50ns delay in series with BCK, then LRK and see how this change or not the output vs SCK...
let see
PCM1794A Adaptor | eBay
and a couple of 4040 an hc04 to make some real experiment.
my plan is to connect a 12Mhz crystal on 4040 then take BCK (Q2) and LRCLK (Q8) and a fake I2S data by using the Q12 (/4096). Hopefully I will get a 3 khz square wave at the output of the PCM (to be loaded by a 100ohms).
I will plug the oscope and see how things are synchronized, then I will put 4 gates HC04 to create about 50ns delay in series with BCK, then LRK and see how this change or not the output vs SCK...
let see
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