The new ESS ES9039Q2M

Has anyone played around with this chip yet? I have some Eval boards here. I’m surprised nobody is talking about the new hardware sync mode that allows you to sync to a local 49.152mhz clock in sync mode. And autodetect the incoming sample rate from the bit clock. There’s also 2 new filters the 9039Pro doesn’t have. And check out the THD+N from the analog outputs of the eval board. After the opamps.

Seems it’s not much different at all. I misinterpreted how it worked based on different explanations in the 9039Pro eval board datasheet, and the 9039Q2M Eval board datasheet. Which was clarified after talking to ESS. I thought it was some sort of synchronous re-clocking setup.

But there is a hardware mode. That should be of interest to Diyer‘s who enjoy the best DAC performance ever seen from any chip, let alone one with an extremely low BOM to achieve the datasheet results. The datasheet specs are actually from the opamp outs of a finished design, rather than the outputs of the DAC chip. That’s the first time I’ve seen that in a DAC chip datasheet. Very few ES9038Q2M implementations come close to the datasheet specs in the finished design.
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Well good measurements don’t automatically mean bad sound. ESS made lots of improvements to the sound with the Hyperstream 4 modulators used in the 9039 DAC’s. And revised the filters. So there’s more improvements to these DAC’s over the 9038Pro/9038Q2M than the THD+N figures alone suggest.

If we look at the SMSL D400 DAC’s for example, they make a version with the 9039Pro and the flagship AKM 4499DX/AK4191 combo. So far reading around the internet, most people who have compared both side by side, subjectivity prefer the ES9039 version.
This is all we are told:

This latest generation of the Hyperstream® IV improves audio performance while consuming significantly lower power compared to the previous generation. This audio performance improvement translates into less digital noise inside the device allowing for the vibrant nuances of the audio to be more “real”.
It’s actually 50Mhz for async mode. 49.152mhz is for a direct clock divide in sync mode for 48 clock multiples. 49.152mhz is all that’s needed for up to 24/768. As that frequency is 1:1 at 24/768. 50Mhz is all that’s needed to create a PLL for all 44.1/48 multiple sample rates compatible with the chip.

50Mhz clocks have lower phase noise than 100Mhz. Dustin chose a 50Mhz master even with his Resonessance Labs DAC’s using the 9018. So he must have felt it was better to change things up for this chip. It might also have something to do with power saving.
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Thanks. IIUC 49MHz is 64 x 768kHz, i.e. corresponding to standard 32bit-wide I2S.

A number of well-measured ESS DAC implementations use 100MHz in async mode, i.e. the DA conversion runs at 100MHz for any samplerate.

Yes, I can imagine the clock was reduced (also) to satisfy the lower specced maximum power consumption.
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