Dear Solid-State wizards,
I'd like to share with you the all-out hexfet CFP design I've been tweaking over the last months. It's been build rather successfully on breadboard and I started the first attempt at a PCB layout. There is however a very large discrepancy between simulated and measured performance, nevertheless it still is rather good.
Perhaps it is unrealistic to expect optimum performance from a breadboard build. I suspect more performance is to be gained from a well designed PCB layout. The Hexfet CFP may be a fundamentally compromised and Sisyphean approach, but I want to follow through and see how far this design can go.
The Wolverine amplifier for example shows lots of performance is to be gained from well routed tracks. In LT spice I've seen that parasitic impedance in the OPS and PSU can make or break the amplifier's performance. Series inductance in the supply lines, ground and in OPS Mosfet drain&source tracks made my breadboard build to require triple the high frequency compensation with respect to simulation. I'm sure there are many more reasons for the performance discrepancy as im not able to close the performance gap completely by adding parasitic's in LT-spice.
If anyone has the time to review my PCB design I would be very grateful. What makes a good layout goes quite beyond me, therefor I would love to hear your feedback and suggestions. I'd like to gain a better understanding of where performance may be lost in PCB design. First let me share the design and measurements.
Much thanks and cheers,
Ruben
The source and measurement device is a Focusrite Scarlet 2i4. I was not seeing major differences before and after the amp so i'm also showing the measurements at the input of the amplifier.
Here is the source FR:
And The amplifier FR:
Amplifier IMD at 9VRMS into 4 ohm:
Source IMD at input:
THD1k 13VRMS:
THD1k at input:
THD5k 13VRMS:
THD5k at input:
I'd like to share with you the all-out hexfet CFP design I've been tweaking over the last months. It's been build rather successfully on breadboard and I started the first attempt at a PCB layout. There is however a very large discrepancy between simulated and measured performance, nevertheless it still is rather good.
Perhaps it is unrealistic to expect optimum performance from a breadboard build. I suspect more performance is to be gained from a well designed PCB layout. The Hexfet CFP may be a fundamentally compromised and Sisyphean approach, but I want to follow through and see how far this design can go.
The Wolverine amplifier for example shows lots of performance is to be gained from well routed tracks. In LT spice I've seen that parasitic impedance in the OPS and PSU can make or break the amplifier's performance. Series inductance in the supply lines, ground and in OPS Mosfet drain&source tracks made my breadboard build to require triple the high frequency compensation with respect to simulation. I'm sure there are many more reasons for the performance discrepancy as im not able to close the performance gap completely by adding parasitic's in LT-spice.
If anyone has the time to review my PCB design I would be very grateful. What makes a good layout goes quite beyond me, therefor I would love to hear your feedback and suggestions. I'd like to gain a better understanding of where performance may be lost in PCB design. First let me share the design and measurements.
Much thanks and cheers,
Ruben
Simplified schematic:
Gain and Phase Margins:
Circuit currently on Breadboard:
Latest Measurements:
Testing using a dualpolar 51V raw supply with 10mF resevoir caps and single rectifier. Load is 4 ohm:10K Clipping:
Rising and falling edges:
Arta Testing with 4 ohm load:
The source and measurement device is a Focusrite Scarlet 2i4. I was not seeing major differences before and after the amp so i'm also showing the measurements at the input of the amplifier.
Here is the source FR:
And The amplifier FR:
Amplifier IMD at 9VRMS into 4 ohm:
Source IMD at input:
THD1k 13VRMS:
THD1k at input:
THD5k 13VRMS:
THD5k at input:
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Here is my first PCB attempt on this circuit. I would very much appreciate your feedback. I understand screenshots might not be clear enough so I attached the KiCAD project as Zipfile.
The PCB's will be sized according to the heatsinks im using. Current board is 94mmX200mm 4 layers. Inner two layers are positive and negative supply voltage planes. Top has signal ground plane and most signal traces. Bottom has a ground plane for capacitive decoupling. The two ground-planes meet at the negative speaker terminal. The PSU will be included on the same board for minimal impedance. The Mosfets are arranged such that the tracks between them can be short. Perhaps there is a better possible arrangement to minimize parasitic's here.
I'm planning to design a little auxiliary SMD DC servo board that will plug into the 2X3 pin-socket. The DC offset is OK but hovers between + and - 20mV.
Also I'm thinking of replacing all compensation caps with pin-sockets such that I can optimize before soldering directly to the board.
I am yet to add SMD decoupling caps at the bottom, tidy up the silkscreen and add mounting holes.
Any thoughts and opinions are welcome.
Much thanks and Cheers!
Ruben
Bottom:
Top:
The PCB's will be sized according to the heatsinks im using. Current board is 94mmX200mm 4 layers. Inner two layers are positive and negative supply voltage planes. Top has signal ground plane and most signal traces. Bottom has a ground plane for capacitive decoupling. The two ground-planes meet at the negative speaker terminal. The PSU will be included on the same board for minimal impedance. The Mosfets are arranged such that the tracks between them can be short. Perhaps there is a better possible arrangement to minimize parasitic's here.
I'm planning to design a little auxiliary SMD DC servo board that will plug into the 2X3 pin-socket. The DC offset is OK but hovers between + and - 20mV.
Also I'm thinking of replacing all compensation caps with pin-sockets such that I can optimize before soldering directly to the board.
I am yet to add SMD decoupling caps at the bottom, tidy up the silkscreen and add mounting holes.
Any thoughts and opinions are welcome.
Much thanks and Cheers!
Ruben
Bottom:
Top:
Attachments
H
HAYK
Your Amp is by far superior to Wolverine. THD numbers don't reflect the sound quality but the loop gain does. @20 kHz you have over 60db VS 24db, make slight more effort to reach 70db and you are in perfection to my experience. Wolverine was not capable of reproducing the requiem of Mozart and My Way of Frank without distorting, I am very sure yours will have celestial voice.
H
HAYK
Paralleled output MOSFETS with only 0.05 ohm source resistors needs matched pairs. Design a lower power version with one pair of outputs without source resistors, it can be more DIY friendly.
Dear Ed and HAYK,
Thank you for the kind words. Me myself is particularly happy about the low inter-modulation and dominant second harmonic.
Bias is adjusted with trim2. Increase the current through the N channel JFET (J3) and the bias drops. Driver and Pre-driver are mounted to the same heatsink to provide thermal compensation. Works beautifully and allows adjustment from 1 amp to no bias with nice linearity. The bias drops a 100mA over an hour but never starts rising again. After continues power it falls back to where it was fairly quickly. There is no temperature feedback from the Mosfets, apparently with this arrangement it is not needed and if anything gives me better bias stability in this instance. Emitter resistors are key here. Big but bypassed.
The source resistors are just there to tell me how the current is shared. I might move them to the drains. I'm quite alright with having to match pairs as finding two similar mosfets is not that hard. A single complementary pair could do for a 50W version. I like to run about 200mA per mosfet so the heatsink should be quite large. A 50W version (into 4 ohms) can be much smaller with lower supply voltages.
Much thanks and cheers,
Ruben
Thank you for the kind words. Me myself is particularly happy about the low inter-modulation and dominant second harmonic.
Bias is adjusted with trim2. Increase the current through the N channel JFET (J3) and the bias drops. Driver and Pre-driver are mounted to the same heatsink to provide thermal compensation. Works beautifully and allows adjustment from 1 amp to no bias with nice linearity. The bias drops a 100mA over an hour but never starts rising again. After continues power it falls back to where it was fairly quickly. There is no temperature feedback from the Mosfets, apparently with this arrangement it is not needed and if anything gives me better bias stability in this instance. Emitter resistors are key here. Big but bypassed.
The source resistors are just there to tell me how the current is shared. I might move them to the drains. I'm quite alright with having to match pairs as finding two similar mosfets is not that hard. A single complementary pair could do for a 50W version. I like to run about 200mA per mosfet so the heatsink should be quite large. A 50W version (into 4 ohms) can be much smaller with lower supply voltages.
Much thanks and cheers,
Ruben
H
HAYK
The base voltages of Q7 and Q8 remain always positive. Maybe the colectors can be grounded and BC560C transistors can be used.
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Very nice , seems to of worked real good. 3 stage differential , surprised you got it stable. I had to use lag and lead compensation where you just
used shunt compensation. 3 stage has crazy open loop gain , this why you get such low distortion. I'm impressed !!
OS
used shunt compensation. 3 stage has crazy open loop gain , this why you get such low distortion. I'm impressed !!
OS
I doubt that. Distorting ?? WTF. I do concede this 3 stage blows the wolverine away in OLG. In fact , I have the "Kypton" which will be one of my 6
IPS's and is similar to this. This particular IPS dates back to a 1970's Sansui amplifier. Imagine that , the Japanese aced this 50 years ago.
Now , you might have more OLG , but it is the quality of the OPS that allows all that extra feedback to have effect. Bet this amp would have PPM
THD at 50Khz !!
Still , a beautiful topology !
OS
Thanks for taking interest!
And precisely.. Its all about finding an OPS thats linear but FAST such that loopgain can act over a larger bandwidth!
Some more info:
The 'spice fantasy' version as initially simulated uses a combination of two pole miller and transitional compensation. Sadly on breadboard this gave oscillation near clipping and on squarewaves. Will still try it on pcb.
Referring to the 2nd schematic as on breadboard:
On breadboard currently im using two pole compensation (comprised of C13, C16, C5, C17 and R11) which should result in about 54dB of loopgain at 20kHz.
The shunt network of R35 and C7 is critical for global gain margin too (to the expense of phase margin and slew-rate). It also helps stabilize the local feedback loop in the OPS. To stabilize the OPS I had to include 6.8 ohms between output and emmiters (R31) another compromise... I think this is due to inductance in the drain and source lines. Bypassing it with a small inductor and some pF capacitor should bring back some performance although I could not verify on breadboard. Other distortion mechanisms are much more dominant. Increasing the LTP and vas current did yield some 0.000X% gains.
I found the top half to be clipping earlier due to a too low voltage mosfet gate protection zener. I upped the value to 8V2 to 12V. Now top clipping looks much better driving 4 ohms:
Here a closer look at step response:
Muchas Cheerios,
Ruben
Could be. In simulation 2N5401C yields lower distortion. Might not translate to real life though.
Currently measure about 2.8mV between them
Yes in simulation loopgain is absolutely savage! I doubt its that high IRL as im running somewhat less LTP current due to temperature. My favorite elements are the IPS drain loads taking their reference from the VAS emitters and the driven IPS cascode. Didnt know Sansui did it in the 70's lol. Which amp?
And precisely.. Its all about finding an OPS thats linear but FAST such that loopgain can act over a larger bandwidth!
Some more info:
The 'spice fantasy' version as initially simulated uses a combination of two pole miller and transitional compensation. Sadly on breadboard this gave oscillation near clipping and on squarewaves. Will still try it on pcb.
Referring to the 2nd schematic as on breadboard:
On breadboard currently im using two pole compensation (comprised of C13, C16, C5, C17 and R11) which should result in about 54dB of loopgain at 20kHz.
The shunt network of R35 and C7 is critical for global gain margin too (to the expense of phase margin and slew-rate). It also helps stabilize the local feedback loop in the OPS. To stabilize the OPS I had to include 6.8 ohms between output and emmiters (R31) another compromise... I think this is due to inductance in the drain and source lines. Bypassing it with a small inductor and some pF capacitor should bring back some performance although I could not verify on breadboard. Other distortion mechanisms are much more dominant. Increasing the LTP and vas current did yield some 0.000X% gains.
I found the top half to be clipping earlier due to a too low voltage mosfet gate protection zener. I upped the value to 8V2 to 12V. Now top clipping looks much better driving 4 ohms:
Here a closer look at step response:
Muchas Cheerios,
Ruben
Where did you get the compensation scheme of C13,16,17,10,5 + R27,11, and 30 ?? quite unique !
Like a 2 pole common mode between the 2'nd and 3'rd stages. The Japanese didn't do this ?
Damn , i did not read the last post ! Interesting !!
Ya gots my attention !
Like a 2 pole common mode between the 2'nd and 3'rd stages. The Japanese didn't do this ?
Damn , i did not read the last post ! Interesting !!
Ya gots my attention !
Some sleepless nights haha. Transitional two pole compensation should be possible don't you think?
On my version of this clipping would bring about ringing to the verge of short term oscillation.
This topology could beat the Wolverine AND match the Halcro with it's superior OLG.
So many nested loops here. I might take a whack at this .... the most interesting design I've seen in a long time.
Transistor defects and millimeter layout screw-ups would be the only limitations to this design elegance.
OS
This topology could beat the Wolverine AND match the Halcro with it's superior OLG.
So many nested loops here. I might take a whack at this .... the most interesting design I've seen in a long time.
Transistor defects and millimeter layout screw-ups would be the only limitations to this design elegance.
OS
No sleepless nights , I've been "around the block". I identified and wrapped my head around your design - quite advanced.
TPC/TMC ... cool , huh !! You are a "wizard" , as well !
OS
Thanks OS!
My first attempts also had bad ringing. When I upped the global compensation, lowered OPS compensation and lowered gate resistors this disappeared.
Proper implementation of this design is gonna be tricky indeed.
Another limitation is that it clips 12V from the supply. Clipping it unchecked will result in much nastiness and possibly damage. Hence Q15&16 for controlled clipping.. When not venturing as close to the rails, I could give the OPS more compensation again without ringing and went back to 100 ohm gate resistors.
Yes it might behave better with EF3, but my simulation results were discouraging. Non-switching and error-corrected scheme like this though.. https://www.data-odyssey.nl/AutoBias_II.html
When the hexfet CFP proves too cumbersome, this is the next OPS ill try.
My first attempts also had bad ringing. When I upped the global compensation, lowered OPS compensation and lowered gate resistors this disappeared.
Proper implementation of this design is gonna be tricky indeed.
Another limitation is that it clips 12V from the supply. Clipping it unchecked will result in much nastiness and possibly damage. Hence Q15&16 for controlled clipping.. When not venturing as close to the rails, I could give the OPS more compensation again without ringing and went back to 100 ohm gate resistors.
Yes it might behave better with EF3, but my simulation results were discouraging. Non-switching and error-corrected scheme like this though.. https://www.data-odyssey.nl/AutoBias_II.html
When the hexfet CFP proves too cumbersome, this is the next OPS ill try.
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H
HAYK
You can make this autobiased by replacing the jfet with an opto coupler activated by two resistors 3.3 ohm paralleled each with 1n5107 diodes measuring the currents of the drains at the output. Use VOS617 opto, it has 150 kHz bandwidth but SMD.