Testing a Reticon SAD 4096 chip

Zero Cool

Paid Member
2004-09-20 6:10 am
Any one have any information on how to test an old Reticon SAD 4096 chip from an analog delay???

It looks like there is one clock line going in and audio in and audio out.
I can confirm that there is a square wave clock signal going in, but i have no idea if it is the correct frequency. adjusting the delay rate changes the frequency of the clock signal.

But out of the chip all i get is HF oscillation. about 28Khz or more so i am assuming of course the chip is bad as these are known to fail.

But, is there a way to test these or bread board up some sort of tester to be 100% sure???



2006-12-28 12:19 am
IIRC the input must be biased at 1/2 the rail voltage and the output capacitively coupled. also i think it used a biphase clock (two clock inputs, 180deg out of phase). i used to have a flanger that used the 1024, and was going to turn it into a delay by swapping the 1024 with a 4096.
Unclejed is correct. The clock inputs must be bi-phase. The clock frequency sets the delay time. The output is also bi-phase to help clock noise rejection.

I have included a test circuit from the Reticon data sheet. I have several designs using the 4096 I did in the late 70's - early 80's. I will try to find one of them and post it for you.


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2006-12-28 12:19 am
i remember that circuit well...... R13 is the output balance, it's what nulls out the clock "carrier". basically there are 2 delay lines (strings of analog sample/hold circuits), each triggered by one of the clock inputs. as each S/H is triggered it passes on it's sample to the next one. when the clock changes state, it grabs a new sample. kind of an analog version of FIFO cache.
switched capacitor filters are kind of the same concept, but different structure to match a different function.

if you could get the clock frequency to ramp rapidly, the SAD4096 will also operate as a pitch changer