Hi
In my new DAC design i plan to use different clocks against the es9018.
I would like to make it possible to easily switch between synchronous and asynchronous clocking.
Effectively this means that i need to be able to control which masterclock the dac is using.
Most audio grade clocks do not have a disable function. The crystek cchd-957 does but that one is not available in 80 or 100 mhz. And i plan to use those frequencies when running in asynchronous mode. The same goes for most femto clocks i found: no disable option.
I have read that some people are using a potato high bandwidth switching ic (PO3B3306A) to switch between different clocks.
Personally i am afraid this will negatively affect the clock signal by introducing more noise. This is something that i obviously do not want.
My question to this forum is whether people know of really good solutions to allow switching between master clocks.
In my new DAC design i plan to use different clocks against the es9018.
I would like to make it possible to easily switch between synchronous and asynchronous clocking.
Effectively this means that i need to be able to control which masterclock the dac is using.
Most audio grade clocks do not have a disable function. The crystek cchd-957 does but that one is not available in 80 or 100 mhz. And i plan to use those frequencies when running in asynchronous mode. The same goes for most femto clocks i found: no disable option.
I have read that some people are using a potato high bandwidth switching ic (PO3B3306A) to switch between different clocks.
Personally i am afraid this will negatively affect the clock signal by introducing more noise. This is something that i obviously do not want.
My question to this forum is whether people know of really good solutions to allow switching between master clocks.
Any active gates between the oscillator and the DAC will degrade the quality of the clock. Furthermore, the unused but still running oscillator will contribute noise via the power rails and ground plane.
Why do you need to quickly switch between different oscillators? If you are evaluating the DAC's clocking methods, switching oscillators at the same time will yield a biased comparison. Use a dual or programmable frequency oscillator to evaluate the method and then, if you still have money to burn, replace the dual oscillator with a fixed-frequency, audiophile-approved, jewel-encrusted, femto oscillator.
Crystek ultra low jitter clocks are based on a NC7SZ400 gate and a NC7SZ126 buffer that has an enable output for placing it in tri-state (floating).
This is the AND gate that crystek uses for its “ultra low jitter” crystal oscillators:
https://www.fairchildsemi.com/datasheets/NC/NC7SZ00.pdf
And this is the tri state clock buffer:
https://www.fairchildsemi.com/datasheets/NC/NC7SZ126.pdf
There is little other option than use similar buffer and connect all buffer outputs in parallel.
Crystal oscillators that already have output enable have this or similar tri-state buffer built-in.
I bought some Crystek crystal oscillators, blinded by the phase noise specs.
I tested crystek CCHD-957 and some smaller Crystek ultra low jitter oscillators. Performance was so bad that I decided to open the housing in order to figure out what was causing this (attached picture).
I doubt if this is an ultra low jitter design, just a plain 00 AND gate and a plain 126 buffer. It is basically similar to standard crystal oscillators integrated in a microcontroller, so really nothing special.
Here is what a true low phase noise designs looks like:
Low Phase Noise Design: Crystal Oscillators
If you are looking for low phase noise SMD crystal oscillator check NDK:
Crystal Clock Oscillators / NDK
D/A converter chips also produce large amounts of jitter (additive jitter) and I2S data interference bleeds through circuit parasitics and causes on-chip deterministic (data related) jitter.
So the I2S interface alone will already cause unacceptable degrading and any D/A converter chip running on such interface is already heavily flawed by design.
In order to get acceptable performance we need "flash loading" of data instead of a continuous serial data stream that constantly produces on-chip interference and related jitter.
Because there are no perfect components and circuits, the phase noise performance of the master clock driving the DAC chip will also be significantly degraded. Stray capacitance of 5pF for example (NC7SZ126 clock buffer) will introduce a bypass impedance of approx. 318 Ohms @ 100 MHz.
This means that the noisy clock load is basically connected directly to the highly sensitive crystal oscillator circuit through a 318 Ohm "bypass" impedance. In that case a clock buffer is not going to be very effective.
These bypass impedances are everywhere and when you redraw schematics including all stray capacitances, stray reactances, DC resistance, coupling (parallel PCB traces), and EMI you will see that the situation gets pretty hopeless.
This is the AND gate that crystek uses for its “ultra low jitter” crystal oscillators:
https://www.fairchildsemi.com/datasheets/NC/NC7SZ00.pdf
And this is the tri state clock buffer:
https://www.fairchildsemi.com/datasheets/NC/NC7SZ126.pdf
There is little other option than use similar buffer and connect all buffer outputs in parallel.
Crystal oscillators that already have output enable have this or similar tri-state buffer built-in.
I bought some Crystek crystal oscillators, blinded by the phase noise specs.
I tested crystek CCHD-957 and some smaller Crystek ultra low jitter oscillators. Performance was so bad that I decided to open the housing in order to figure out what was causing this (attached picture).
I doubt if this is an ultra low jitter design, just a plain 00 AND gate and a plain 126 buffer. It is basically similar to standard crystal oscillators integrated in a microcontroller, so really nothing special.
Here is what a true low phase noise designs looks like:
Low Phase Noise Design: Crystal Oscillators
If you are looking for low phase noise SMD crystal oscillator check NDK:
Crystal Clock Oscillators / NDK
D/A converter chips also produce large amounts of jitter (additive jitter) and I2S data interference bleeds through circuit parasitics and causes on-chip deterministic (data related) jitter.
So the I2S interface alone will already cause unacceptable degrading and any D/A converter chip running on such interface is already heavily flawed by design.
In order to get acceptable performance we need "flash loading" of data instead of a continuous serial data stream that constantly produces on-chip interference and related jitter.
Because there are no perfect components and circuits, the phase noise performance of the master clock driving the DAC chip will also be significantly degraded. Stray capacitance of 5pF for example (NC7SZ126 clock buffer) will introduce a bypass impedance of approx. 318 Ohms @ 100 MHz.
This means that the noisy clock load is basically connected directly to the highly sensitive crystal oscillator circuit through a 318 Ohm "bypass" impedance. In that case a clock buffer is not going to be very effective.
These bypass impedances are everywhere and when you redraw schematics including all stray capacitances, stray reactances, DC resistance, coupling (parallel PCB traces), and EMI you will see that the situation gets pretty hopeless.
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