Strange Teac DAC

Hi,

again, what happens here in my 1 x PCM53 for both channels TEAC ZD700 ?
Still I do not understand the circuit except that left and right must be separated.

Is this non-os ?
In pic 1 the sine consists of 44 spikes, and
in pic 3 there are 44 stripes on the bargraph inside a 1kHz sine = 44 kHz ?
Sine is 0 dB.
The bargraph remains when player is on pause.
Is the bargraph some kind of help-signal ?

Schematic + scope pics:

TEAC_1.jpg


TEAC_2.jpg


TEAC_3.jpg


TEAC_4.jpg


TEAC_5.jpg


TEAC_6.jpg


TEAC_7.jpg


TEAC_8.jpg


teac.jpg
 
Thanks,

looks really like decimation and maybe they applied also dither,
the bargraph is noisy and when I look at the schematic now spontanously I see the following possibility:

the switch close to 6 removes the audio samples from the signal, leaving the noise and the inverted noise is added to the original signal so that the noise cancels :D at the resistor bridge at 7.
I made mistake reading the values it is 15k, not 150k. Very small resistors...

Now is that decimation done in the analog or digital domain ?

The low level performance of that DAC is the best of all multibits I have seen and I want to built it with two DAC chips but now it becomes tricky...

Is there a way to use the left deglitch and right deglitch signals to separate the left/right data for two DAC chips ?

Comments ?
 
guytou said:
isn't your sheme a simple sample and hold for early 1DAC/CDP's ? It could'nt be decimation here because decimation operates in the digital domain , no ? Wich DF is before the DAC ?

Usually S/H is only 2 x S/H for early 1DAC/CDP's like indicated as functional unit around 1 in the schematic.
All those circuitry that I have drawn detailed in the schematic, I have never seen in any datasheet of old DAC chips like PCM53, 54, 56...

Maybe it is not decimation , when I make the S/H cap very small around 220pF, it looks like 1 before the filter also in my 4 x os PCM53 DAC that I built for testing.

When adjusting the pots there is pink noise that can be adjusted to disappear, so there must be something like dither.

The OS chip is TEAC 52200492-00 :D
 
rfbrw said:



From what dataflow?

rfbrw,

you are one of the great Manitou here :D,
don`t you have an idea about this circuit ?

Is it possible to feed the parallel 16bit data from that TEAC chip to a pair of latches and update the contents of the latches with the two deglitch signals ?

Or split the left/right data before the TEAC chip and use two chips.

Denon DCD1500 also uses a pair of mono os filters SM5801, but PCM53 is not good with them.
 
Bernhard said:
Do you have this player ? Any picture you can post ?
Maybe bigger schematic also of the output section and more of the digital part ?

Hi,

I have a few old CD 501s. That model was the first Tascam professional CD used at my radio station. I still may have some schematics if you're interested.

But impossible to build without that big chip. [/B]

I have "that big chip" somewhere in my parts bins. Send me PM.

Regards,
Milan
 

rfbrw

Member
2001-10-26 11:51 pm
.
Bernhard said:

rfbrw,
you are one of the great Manitou here :D,

You appear to have mistaken me for KYW or Ulas


don`t you have an idea about this circuit ?
Is it possible to feed the parallel 16bit data from that TEAC chip to a pair of latches and update the contents of the latches with the two deglitch signals ?

Or split the left/right data before the TEAC chip and use two chips.

Denon DCD1500 also uses a pair of mono os filters SM5801, but PCM53 is not good with them.

I have little or no information about the chips you are using and more to the point I do not have the slightest idea as to what it is you are trying to do. Are you modifying an existing circuit? Are you trying to copy an existing circuit? Are you building a new circuit based on Teac's circuit? Is this your first visit to Earth?
If all you want to do is build a dac using the PCM53 then there are a number of possibilities open to you all using fairly standard components.

guytou said:
Hi rfbrw , the serial/parallel dataflow,if i am right , i.e. the one that comes from YM3613/CXD2500 decoder .

If all you want to do is convert an alternate L/R data stream into individual simultaneous L and R datastreams, then there are at least three circuits in the forum.
Search for Nonos PCM1704 for a place to start.
 
rfbrw said:


I have little or no information about the chips you are using and more to the point I do not have the slightest idea as to what it is you are trying to do. Are you modifying an existing circuit? Are you trying to copy an existing circuit? Are you building a new circuit based on Teac's circuit? Is this your first visit to Earth?

The chips I used was SM5813 & SM5803 with PCM53 in 4 x & 8x OS, seriell to parallel conversion done by a DENON chip.
I want to build a new DAC with 2 x PCM53 instead of only 1xPCM53 as is in the TEAC CDP.
But it seems that the good low level performance of that CDP is not based on the PCM53 but on the TEAC ZD design - what ever that is - dither, noise added before DAC and removed after DAC, or decimation...

So now I can try to get the big chip from the Tascam CD501 but it is not sure that this chip is also non-os like my TEAC and performing as good, also input signals might not be standard.
Also noise might be added somewhere before but the chip is named adder in the schematic.
Lots of variables...

Or I try to get the whole Tascam CDP.

Or somebody gives me a hint how to split the alternating left right data ( parallel format ) that comes from the TEAC chip inside my CDP and feed it to latches, and generate new deglitch signals.

Inside my CDP there is this TEAC chip that has seriell input from a sony CX chip and parallel 16 bit data output to the PCM53 and three different deglitch signals, two for left right splitting and one for the mystery noisecancel circuit.

Low level performance was always bad in my PCM53 implementations, last chance is to try non-os, otherwise it depends on the TEAC ZD.
 

rfbrw

Member
2001-10-26 11:51 pm
.
You need to draw a timing diagram showing the position of where the data is relative to where you want it to be. From that you will see that you need 2 16 bit shift registers and maybe a binary counter or two. As both channels are in the same time frame you won't have to generate a new DG signal. Just use the normal DG signal and adjust its position depending on the latency of the data. S