I've been pondering making a design for a discrete op-amp. Something that is not too complex and yet offers performance as good as IC op-amps.

Attached is one design I am considering (only simulated at the moment - it's too damned hot to do any real work). It has a single-ended input instead of differential for simplicity (lower component count plus no need for Miller compensation). This makes it 'current feedback' (as in low-impedance feedback node - not to be confused with 'current feedback' meaning feedback proportional to output current).

Biasing for the Vas is accomplished with current mirrors. This helps with symmetry, in particular compensating for the potentially unequal Vgs of the two Vas JFETs.

Both the input stage and Vas are cascoded, which in conjunction with the current mirrors provides both constant current and constant voltage operation for those transistors, minimizing thermal memory distortion.

Output stage uses JFETs, for simplicity.

Simulated performance compares well with IC op-amps, with 134dB of open-loop gain, 30MHz GBP, very high input impedance, low output impedance, low distortion and around 180V/us of slew-rate. It's not quite as simple as I had set out to create, but it's not too bad.

Comments and criticism welcome!

Attached is one design I am considering (only simulated at the moment - it's too damned hot to do any real work). It has a single-ended input instead of differential for simplicity (lower component count plus no need for Miller compensation). This makes it 'current feedback' (as in low-impedance feedback node - not to be confused with 'current feedback' meaning feedback proportional to output current).

Biasing for the Vas is accomplished with current mirrors. This helps with symmetry, in particular compensating for the potentially unequal Vgs of the two Vas JFETs.

Both the input stage and Vas are cascoded, which in conjunction with the current mirrors provides both constant current and constant voltage operation for those transistors, minimizing thermal memory distortion.

Output stage uses JFETs, for simplicity.

Simulated performance compares well with IC op-amps, with 134dB of open-loop gain, 30MHz GBP, very high input impedance, low output impedance, low distortion and around 180V/us of slew-rate. It's not quite as simple as I had set out to create, but it's not too bad.

Comments and criticism welcome!