replace DAC

Compairing the two data sheets I don't think it will work. The reason is that the Samsung DAC uses two word clocks; one for left and one for right and they are not present for a complete cycle of the data. I have never seen this before.

The Ti part uses the industry standard method of having one word clock with left indicated by one state of the line and right by the other.

If you are good at logic circuits it may be possible to create a circuit to convert the two word clocks into one that is compatible with the TI chip.

Regards,
Andrew
 
For the samsung part the timing diagrams show the two left right word control clocks WDCLK1 and WDCLCK2 clocks on page 508 in both timming diagram 1 and timming diagram two.

For the BB part the timming diagrams are on page 15 and show just one combined LRCK for left and right word control.

Regards,
Andrew
 

maxpou

Member
2006-04-02 7:17 pm
Québec
Thank you guys for reply,
but you need a other document sorry! In my cd player the dac use only WDCLK1 as in this schematic.

rfbrw: can you explain more because i don't understand?
thnak you! maxpou
 

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error401

Member
2007-03-24 7:54 am
maxpou said:
Thank you guys for reply,
but you need a other document sorry! In my cd player the dac use only WDCLK1 as in this schematic.

rfbrw: can you explain more because i don't understand?
thnak you! maxpou

There are two WDCLK modes for this DAC. See the timing diagram headings, the modes are selected by MS. When MS is high, WDCLK is just LRCK * 2. You can probably just ignore this though, since it's not needed for the TI DAC.

As rfbrw says, all the signals you need are there (LRCK, BCLK, DIN) except for the system or master clock input. I think you can find that on the SM5807 XTI pin. It should be 16.9344MHz, which is suitable for PCM1754. PCM1754 can run at 5V, so level shifting is not required. I think this should work without much trouble, but obviously you need a whole new output stage.
 
Hi
error401 said:


There are two WDCLK modes for this DAC. See the timing diagram headings, the modes are selected by MS. When MS is high, WDCLK is just LRCK * 2. You can probably just ignore this though, since it's not needed for the TI DAC.


As rfbrw says, all the signals you need are there (LRCK, BCLK, DIN) except for the system or master clock input. I think you can find that on the SM5807 XTI pin. It should be 16.9344MHz, which is suitable for PCM1754. PCM1754 can run at 5V, so level shifting is not required. I think this should work without much trouble, but obviously you need a whole new output stage.

How should selected the FMT pin in PCM1754?

i forgot to tell you i don't have the digital filter (sm5807). I changed my output stage with only a jfet source follower.
Thank you! Maxpou