Questions about programming the sync mode for ES9038Q2M and ES9039Q2M

[Tfive]

HI there,

I'm currently writing controller software for ES9038Q2M and ES9039Q2M DAC chips. Hardware is not up yet, so I cannot test but if possible I want to finish the controller software beforehand. I have some questions on how the "sync" mode (128fs mode) mode works on both of them.

1. ES9038Q2M:
   The datasheet says you need to set bit 4 of register 10 (128fs_mode, page 24) and disable DPLL, so you need to set register 12 bits 7:4 to 0 (page 26). AFAICT that's all that's needed. You then need to supply a MCLK of 128*FS, so for example a 24.576 MHz clock for 192 kHz sample rate. So if I would supply a 49.152 MHz clock I need to set the MCLK divider to 2 (register 0, bits 3:2, set to 2'b01, page 15)?
   
   
2. ES9039Q2M:
   The datasheet tells me to set bit 6 of register 1 to 1 (page 53). As far as I can tell clock divider ratio will be determined automatically by the chip, at least that's how I interpret the description of register 3 on page 54:
   Automatically determine optimal (MCLK/CLK_IDAC ratio) according to detected FS.
   • 1'b1: Enabled, overrides reg 3[5:0] SELECT_IDAC_NUM (default)

Looking forward to some clarification 🙂

 

[bohrok2610]

I haven't used ES9028Q2M but ES9039Q2M works as you described so I only set bit 6 of register 1. I have used ES9038Q2M which is similar to ES9028Q2M but it has separate setting to enable/disable ASRC (bit 7 in register 27). In ES9038Q2M sync mode works also with 256fs and 512fs MCK.

 

[Tfive]

OMG, I made a massive booboo 🙂 I meant to say ES9038Q2M, dooooh. I revisited the datasheet for ES9038Q2M, now I realize that I looked at the wrong datasheet when describing things here but I looked at the correct datatsheet when implementing my stuff.

So:

• Register 12 DPLL bandwith bits 7:4 set to 0b0000 => DPLL off IMHO still stands
• Register 27 bit 7 set to 0 => ASRC off was added to my code, thanks for that hint!

Also thanks for the hint that ES9038Q2M also works with 256fs and 512fs MCK. I guess it does the clock dividing also automatically then. Will correct original post...

EDIT: please forgive me, several hours of coding late last night lead to some inattentive behaviour on my side 😉
EDIT2: I now realize that the MCLK divider to 2 (register 0, bits 3:2) only applies to I2S master mode which is completely irrelevant in this case.

 

[rfbrw]

Hardware is not up yet, so I cannot test but if possible I want to finish the controller software beforehand.

This is one thing those cheap boards are quite useful for.

 

[IVX]

Did you guys notice that 9039q2m has some undocumented "interpolation free" option in IDAC_NUM reg?
My scope shows me real level-steps at 48kHz, check this out. BTW, I hear no difference(THD@BW20k as well the same) vs normal mode:

 

[bohrok2610]

Have you checked from register 239 that the CLK_DAC/CLK_IDAC ratio is valid?

 

[IVX]

nop, just sending a byte variable(by the Tweak_Cosmos.exe) into the reg and found that.

 

[Dimdim]

I have observed the same behavior on the 9028Pro / 9038Pro, with 128fs mode enabled.

It looks like NOS, even though the different digital filters are still active.

Note that it comes with the classic NOS artifacting in the high frequencies. Doing a frequency sweep easily reveals that.

Plus almost sure it has the NOS high frequency roll-off (to be confirmed with measurements..).