QA-550 SD card 16/44.1 WAV transport

At the Ultimate Source thread, someone asked :

> could you please post a picture of the system e.g. the I2S interface of the QA550.

You can see that clearly at the bottommost photo (attached here) at their Chinese website:

http://www.qlshifi.com/wzcp/QA550.htm


Patrick
 

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jkeny

Banned
2007-02-06 12:43 am
Dublin
That's neat - providing IIS out directly, using os-con caps - this was obviously developed by someone listening in to DIY Audio forums?

It's great to see new, innovative audio solutions arriving, especially as they are keenly priced. Another one from China is the Musiland 24/192KHz USB controller/DAC. These are notably based on DSP or FPGAs and seem to be all the better for that.

Some questions
- are these IIS signals coming from the dsPIC chip? It seems like a longish distance for high speed signals to travel particularly past the screen which is probably radiating noise & then through a lead to a DAC. Jonners, you are running I2S to DAC - no problems?

- Is the chip powerful enough to be able to handle high-res audio? (I know it would be a different design but just wondering). What about USB or ethernet?

- Patrick, Any sound evaluation of it yet?
 
Patrick -

Referring back to your calculation of jitter in the 'ultimate source' thread:
You said:
0.5% of 1/11.2896MHz = 0.44ps
By my calculation that's 440ps.

jkeny -

I2S to TDA1543 DAC works fine for me and sounds at least as good as my 'Shigaclone' transport. My external wires connecting the I2S out to the DAC are at present more than 4" long but I plan to make them very short by having the DAC in a case directly underneath the QA-550.
I haven't traced the internal route of the I2S signals as yet.

John
 
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jkeny

Banned
2007-02-06 12:43 am
Dublin
Thanks Jonners,
For helping out the lazy ones who didn't even bother to redo the jitter calculation. Hmmm, could it be brought lower?

The Musiland USB DAC (from China also) is showing a provisional jitter figure of <100ps (limit of test equip). The Xilinx FPGA used in it - worst case jitter is 150ps (but this is at 200 -300MHz & all gates firing. Real world case 48MHz (on only some parts) & only a few gates firing.
 

jkeny

Banned
2007-02-06 12:43 am
Dublin
Thanks Jonners,
For helping out the lazy ones who didn't even bother to redo the jitter calculation. Hmmm, could it be brought lower?

The Musiland USB DAC (from China also) is showing a provisional jitter figure of <100ps (limit of test equip). The Xilinx FPGA used in it - worst case jitter is 150ps (but this is at 200 -300MHz & all gates firing. Real world case 48MHz (on only some parts) & only a few gates firing.
 
- are these IIS signals coming from the dsPIC chip? It seems like a longish distance for high speed signals to travel...
Yes, they are, and the distance is not too short. And, btw, this is not any kind of DSP but quite an ordinary micro controller.
I neither have very much confidence in routing those I²S signals this way. I am thinking of removing the 74HVC04 and replacing it with an LVDS driver, connected to a RJ-45 socket. Won't be a drop-in replacement, but most probably worth the effort.
 
Is it not better to reclock all lines with D-Fliflops ?
Maybe, this is also an option. In this case, you don't care for signal quality and refresh the signals at the and of the line. The other possibility is not to let the signal quality go down. As I see it, the best error correction is not to let the error happen - but this is theory.
BTW Holger, I did finish that discrete opamp phono.
Great! BF862 still the way to go?
 
Any D-Flipflop will do in principle. The QA550 has 3.3V digital outputs, so you can also use LVDS as well as VHC.

As to the clock, I presume you might want to keep the original one, in which case you can use the MCK output from the I2S of QA550 to drive your Flipflop.

Don't be shy to ask Clark of QLS. he knows his stuff, and is quite willing to help.

If you really want expert advise, go to the other place and ask Jocko or Elso.


Patrick