The lower IRFP9240 [M1] in the above schematic has an idle Vgd~zero V
Yes, but it has a Vds of -4,4 volts and will be linear down to about -1 volt drain-source.
This enables the bottom p-channel fet to swing 6,8 volts into the source of M2. The bottom P-channel fet is a buffer for the positive feedback. Usually the large Vgs of normal enhancing mode switchfets like the IRFP series is a drawback. Here it is a feature as it enables it to be dc coupled to the sensing fet. A logic level gate fet like the IRL series would not be as suitable as there would be much less available voltage swing without some kind of level shifting.
If you want to you can always bias the M1 fet with some kind of voltage source like a battery or some resistor dividing setup and couple the positive feedback through a capacitor to the gate of the M1 p-channel fet, but I see no need for the added complexity and increased parts count.
I think the use of the large Vgs of switchfets as a level shift is turning a disadvantage into an unexpected advantage.
It is all about turning the characteristics of the parts into synergistic effects to minimize parts count and maximize performance. Using the disadvantages in a new way so to mitigate their effect or even make them into advantages.
The bottom p-channel fet is a like one leg of a long tail pair, the other leg of the long tailed pair being the M2 gain device. The source of the p-channel M1 ties into the source of the main gain-device M2. M1 buffers the positive current feedback and drives it into the gain device from a very low impedance source.
If you short out the sensing resistor the M1 p-channel fet will act as a low impedance connection to ground. It is like a voltage regulator.
Cheers,
Johannes