PLL 4046 sanity check please

Hello:

So I am building an application specific oscillator, and have attached a partial (work in progress) schematic. It is a straightforward N=128 frequency multiplier synced to the AC line, with an output freq of 7.68 kHz. I am really interested in anyone's experiences with the low pass filter for the phase locked loop. I have looked into numerous app notes and schematics off the web for simple equations to help me design the LPF without having to go back to feedback control systems.

I have found examples of resistors in the LPF that vary from 1 Meg to 5k, with similar valued capacitance and similar frequency ranges. It appears there is not a lot of consistency. I have used the equations provided in Philips 74HC4046A http://www.datasheetcatalog.org/datasheet/philips/74HC4046A.pdf, and came up with the attached results. Do they look reasonable? I don't need extremely fast settling time; just a stable lock to 60 Hz.

VCO output = 70 Hz at 4.1V
VCO output = 50 Hz at 0.9V

Kp = phase comparator gain = 5/(4pi) = 0.4
Kv = VCO gain = (2fL * 2pi)/(4.1-0.9) = 5026
Kn = 1/N divider ratio = 0.0078125

choose settling time = 0.25 sec, damping ratio 0.7

wn = 5/settling time = 20

t1+t2 = Kp*Kv*Kn/wn^2 = 0.039 sec

select C2 = 1.5 uF

R4 = [(t1+t2)*2*wn*DF - 1] / (Kp*Kv*Kn*C2) = 3.9k

R3 = t1/C2 - R4 = 18.2k
 

Attachments

  • osc2.pdf
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Well, never mind I guess :rolleyes:

Got it dialed in very nicely. Fast settling time, very little overshoot, and extremely clean sine wave output for the application.

PLL equations only get you in the ballpark; you have to adjust by test for optimal performance.

Now on to the power inverter.
 
Old project, but works like a champ.
Latest schematic attached. I used a switched capacitor filter to convert the square into sine. After this circuit, I feed a Class-D power amp and step-up transformer to 120V, so after those components I have no purpose in ultra-low distortion of the SCF.
The addition of MC14557 allows variable phase shift, so you can how tune not just the lock, but the phasing from 0-360 degrees from the original input.
 

Attachments

  • schematic.pdf
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