The roots of this design can be found in a sticky thread at www.diyaudio.com. Somewhere around page 65, a new symmetrical design was published, in an attempt to solve the well known VAS bias instability that usually plagues such a design. The solution was there to add diamond style current sources, defining a constant voltage drop at the input of the emitter follower that isolates the input stage to the VAS. This solution was heavily criticized as being suboptimal, mainly because the input stage voltage gain was limited by the relatively small resistor (load) required to set the VAS bias.
Several improvements were suggested. Edmond published his approach, built around what was eventually defined as Common Mode Current Loop (CMCL) to stabilize the VAS bias (also avoiding the “fighting VAS”, a potential issue in fully symmetrical designs) and a NDFL (also see the references in this article) approach to improve the frequency response of the negative feedback loop over the classic one or two pole compensation.
Ovidiu was lurking around and, after breadboarding the original circuit (with mediocre results, given the project scope), was interested in Edmond’s approach. He breadboarded Edmond’s design, integrated with the already existing Error Correction (EC) based Output Power Stage (OPS) and reported back some issues regarding the thermal stability of the circuit. Which triggered several full redesigns and ultimately to the circuit presented here
A very nice design indeed! - good to see it finally completed.
Just one niggle:
The circuit I presented was actually devised to enable the trouble free use of current mirrors to provide push-pull drive to the VAS miller compensation capacitance in a circuit with a fully symmetrical LTP input. Despite the heavy criticism it actually works quite well (~10ppm THD-20 in the basic 12W prototype built). I really don’t think that it can be fairly compared to a NDFL circuit with biasing servo loops and 10+ times the component count.
Edmond Stuart said:
First, don't feel offended, at least not by us. We only mentioned your amp because it just triggered the whole story. So be glad. Without your input, much chance that history went a different way and our project was never born.
Second, the actual number of trannies in the front-end don't differ that much. In your 12W amp 28 and in our amp 34 (not counting the trannies in the +/-24V PSU and clipping indicator)
Admittedly, the circuit is complex, but who cares about the cost of some additional small signal trannies.
Last but no least, there is no free lunch. You will always need more components in an attempt to reduce the distortion considerably.
BTW, the THD-20 of the front-end (simulated) is < 50ppb, that's why we need so many trannies.
I don’t think that you can discount the trannie count of your modulated PSU though, as it is integral to the performance of the design due to the front-end’s low PSRR
Isn’t the real factor at play here the significantly extend NFB factor out to 20kHz and beyond enabled by the NDFL?
syn08 said:While in principle I agree with you regarding the THD20, at these levels it is though unlikely you could simply divide the OPS open loop THD to the loop gain. If I recall correctly, the loop gain at 20KHz is about 60dB. If you divide the 80ppm (the THD 20 of the open loop OPS) by 1000 you would think you'll get a THD20 of 80ppb, which is simply not happening in the real life. The measured values are one order of magnitude higher.
syn08 said:And BTW, this amp has much more than high loop gain and low THD20. See the pulse response and the comments about the non slewing characteristic and the low TIM and DIM. [/B]
Suppose that your 80ppm THD-20 OPS was combined with a non-NDFL, 80ppm THD-20 front end compensated for a 40dB 20kHz negative feedback factor as described above, and that the THD reduction was commensurate with the loop gain.
So we have 80ppm (front end) + 80ppm (OPS) divided by 100, giving a THD-20 of 1.6ppm. Suppose that we could make the front end infinitely linear – the THD could only be reduced by one half to 0.8ppm (0ppm+80ppm/100).
I think you are oversimplifying a little... From a statistical perspective, adding the squares of the THD numbers would be correct, but this is again only a statistical approach. At very low levels, a realization (read: measurement) of this stochastic process could be largely different! It all depends on the phase relationship of the harmonics produced by the front end vs. the harmonics produced by the OPS. So the correct approach is to add the complex FFTs rather than the THD squared numbers.
But then I agree that the EC OPS in conjunction with a "standard" front end will still deliver impressive performance. But that's precisely why there's a barrier at 1ppm. You can't break it by conventional methods. And you know how these things are going, over a certain level, every 10% improvement may double the complexity/cost.
G.Kleinschmidt said:G'day Edmond
I agree that a handful of cheap transistors isn�t something to worry about. I just don�t think that the performance of the circuit is particularly mediocre for what it is. Throw in EC and NDFL and you can of course expect at least an order of magnitude reduction in THD. I don�t think that you can discount the trannie count of your modulated PSU though, as it is integral to the performance of the design due to the front-end�s low PSRR
50ppb THD for the front end sure is impressive and quite an achievement � congratulations! But a serious question � since the THD performance of just about any well designed class AB power amplifier is dominantly governed by the output stage THD, in the whole scheme of things, does it really matter that the front end THD be thousands of times smaller? Isn�t the real factor at play here the significantly extend NFB factor out to 20kHz and beyond enabled by the NDFL?
That's an interesting result. 80ppm THD-20 for the class AB output stage is quite impressive though. But this leads to some further pondering. If the 80ppm THD-20 output stage was simply added to a much simpler, conventional (non-NDFL) front end compensated for a gain crossover of 2MHz for a 20kHz negative feedback factor of 40dB, would the THD result be largely the same?
Why don't you have the URL in the signature and/or enable your WWW button?Edmond Stuart said:
Edmond Stuart said:
Actually you are right, the modulated PSU is an integral part of the front-end. Perhaps this PSU might look over-engineered, but as a matter of fact, this setup saved us a couple of transistors, as the traditional approach, eight CF cascodes and a conventional +/- 24V PSU, is more complex.
>front end THD be thousands of times smaller?
Where is your math? the 50ppb THD was simmed and I expected 100ppb = 0.1ppm in real life. Our target was a thd20 below 1ppm for the whole amp, so striving for a ten times lower distortion of the front-end is not that outrageous. Besides, we will also use the same front-end in future projects with even lower distortion output stages.
Success with your amp.
PS: Per-Anders, Giaime and Any, thank you!
For those who missed the link to our website, here it is again:
Edmond Stuart said:
It doesn't work that way. To predict the closed loop THD, you must look at the loop gain at frequencies of the harmonics in stead of the fundamental.
Suppose the TDH20 distortion of the OPS consists of only the third harmonic, then we must look at the loop gain at 60kHz. Given a gain crossover of 2MHz and a roll-off rate of 6dB/octave, we get 33.3x or 30.5dB (not 40dB). So the final distortion is 80ppm/33.3= 2.4ppm and not 0.8ppm.
BTW, there seems to be some confusion about the distortion of the front-end. The 50ppb figure refers to simulated closed loop distortion of front-end plus an ideal OPS to provide the FB signal.
peranders said:Why don't you have the URL in the signature and/or enable your WWW button?
Have you gotten any feedback from Mr. Cordell himself?
Maybe this design could be equally famous as Mr. Leach's?
From the little I have seen, the pcb's looks very fine but I can't say how the "micro details" are. 100% OK, some bugs maybe or possible areas of improvement.
Impressive, however, look at pages 10 and 11 of Bobs MOSFET EC amplifier paper - Bobs open loop EC output stage THD-20 was somewhere in the vicinity of an order of magnitude greater than yours (which I am informed is 80ppm [0.008%]).
G.Kleinschmidt said:Hi Edmond.
I agree. I'm probably not helping my argument by simplifying things excessively. I'll try to explain a little better:
I just used the 2MHz unity gain crossover as an example as that is what is what Bob used in his design – not because 40dB loop gain at 20kHz correlates to your 20kHz THD reduction.
Since the MOSFET EC OPS of your design is based on Bobs design, it is reasonable to assume that it too would function with sufficient phase margin and stability with a 2MHz unity gain cross over also.
Bobs design measured 6ppm THD-20. Your amplifier measures 7.5 times less at 0.8ppm.
Impressive, however, look at pages 10 and 11 of Bobs MOSFET EC amplifier paper - Bobs open loop EC output stage THD-20 was somewhere in the vicinity of an order of magnitude greater than yours (which I am informed is 80ppm [0.008%])
I see little reason to believe that if Bob had put as much effort into refining an EC output stage for his amplifier as you guys did, that the THD-20 performance of his design would lag yours by much at all. I definitely can see your ultra low THD front end providing a greater scope for even more impressive performance with even better output stages, but I’m not convinced that such an elaborate front end design (or even NDFL) is necessary to hit the 1ppm THD-20 mark.
I think that my conviction that the OPS is the dominant ogre here stands