Output stage opinions

Hi

Recently I have successfully used an output circuit similar to Mr. Cordell's Hex-Fet EC output stage. I have made some modifications, on paper, to my circuit that I think may work better. The VAS is biasing the +/-11V DC and provides up to +/-22V signal swing (up to 33V) max, adequate for clipping.
My thoughts are to use higher frequency, small signal transistors to increase the bandwidth of the error correction amplifiers. Also, I added a cascode for the first pre-driver and last driver transistors so as to have a constant Vce, and to be able to use small signal, low noise, fast devices for these and still be well within their SOA. The output fets have a Vgs threshold of about 3.5V. The two Vgs multiplier transistors (SOT-23) could be mounted so as to be in contact with the drain lead of the output transistors to sense die temperature. Something like this example
I am thinking it should work well, but I thought I might try to get a second (or more) opinion. Is there any reason this wouldn't work?:scratch:

The transistors I plan to use are:
KSC2223
MMBTH81
FJV1845
KSC1845
KSA992
FJV992
BC850
BC860

and these 'space savers' from On-Semi, labeled 1/2 and 2/2.:
EMX1DXV6T1-D
EMT1DXV6T1-D

Thanks
:cheers:
 

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