OP stage biasing

What's the simplest way to add reliable biasing to this OP stage?
(The VDC will probably be double, ~36-40V)
 

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Lateral mosfets are of different construction than the IRF types. If it doesn’t mention anything about “lateral” on the data sheet, it isn’t.
Lateral mosfets are GSD and vertical mosfets are GDS.
The Hitachi lateral mosfet datasheet uses a 1K pot to bias the laterals.
For bipolar or vertical mosfets a Vbe multiplier is best.
 
Temp Co of enhancements aren't that bad actually
less than BJT.
VBE multiplier could work , numerous circuits to help them
not overtrack. Since temp co of BJT is different.

For such a simple circuit actually diodes would work.
People usually freak out over diode thermal tracking.
This case would help not to over track.

Far as the output topology shown doesn't look too impressive.
But to use all N channel devices you need Quasi design.
Maybe find something different if you require more power.

Far as the one and only Nelson Pass.
Should check out his mosfet version
of the Citation 12
 
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This datasheet shows clear signs of Spirito instability in the SOAR plot: https://www.st.com/resource/en/datasheet/irf630.pdf while this one doesn't: https://www.vishay.com/docs/91031/irf630.pdf In both cases, nothing is specified for pulse widths above 10 ms.

Just for clarification: Spirito instability is a kind of thermal second breakdown that many modern power MOSFETs, especially switching devices with very low on resistance, suffer from. Above a certain drain-source voltage and drain current, a MOSFET with Spirito instability may destruct itself even when it is cooled well, the power dissipation is within the allowable limits, and the external circuit ensures the total current through the device is fixed to some value well below the maximum current rating and that the voltage stays below the voltage rating. If the manufacturer characterized the MOSFET properly, it is shown in SOAR curves as regions where the allowable current decreases faster than inversely proportionally with voltage.
 
Firstly, thanx for the pointer to the Spirito instability problem! Very interesting. Perhaps DIY audio needs a list of MOSFETs to avoid?

Now about the crude amplifier from http://www.hawestv.com/amp_projects/amp_solid_tube/compl_output1.htm
These amps use RC coupling so the upper FET should be biased with a VCC/2 voltage (+4V vto), ie no pot required. The lower FET should probably have a source resistor. A typical bjt current source might be fine because it has a negative temp co. Or a VBE multiplier with a build out resistor to avoid shorting the gate drive. The amplifier needs a better VAS which would help choose how to drive the lower N channel FET. The typical quasi MOSFET output wastes about 4 Volts for the gate threshold, so this RC circuit is hardly worse. Today, P-channel MOSFETs are not difficult to obtain, so quasi designs are perhaps a waste of time. It is important to bootstrap both sides of the output to avoid wasting output swing on the gate threshold bias. I think Miles has some simple MOSFET amps posted here in DIYA.
 

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