# New digital XO project

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#### borges

For a while now I have been working on a CD player project. One of the features I have in there is a Xilinx FPGA to do the digital filtering, 4 audio output channels based on pcm1704 (for fully differential) audio, Tent oscillator etc.

What I did with the fully differential outputs was to also attach phono connectors so that I can run 4 independant audio outputs. So what would be more natural than putting a digital XO into the FPGA?

My problem is where to start. I know nothing about loudspeaker design and XOs. But I do know a fair share about analog and digital filter design in general. So I'm happy about any comments you may have on my ideas here! Also, I'd like to know where to start to learn more about XO design and the way the filters interact with the box and speaker element.

My initial philosophy is to use Laplace equations that add to 1. In the world of analog filters this is only possible with the 1st order lopass and hipass 1/(Ts+1) + Ts/(Ts+1) = 1.

But when going digital, it is possible to come up with Laplace equations that don't map to actual RCL structures, but that can still be transformed to the Z domain using bilinear transform etc.

One of the structures I thought about is to have a denominator of (Ts+1)^n. With n=3, lopass and hipass filters can look like this: (3Ts+1)/(T^3s^3+3T^2s^2+3Ts+1) and (T^3s^3+3T^2s^2)/(-same-denominator-). These two have 2nd order slopes and linear summation. They have a small overshoot. For higher order slopes, use n=5,7,9 etc. For a different overshoot change the denominator from 1-3-3-1 to 1-5-5-1 etc.

But rather than go for a strictly mathematical model I'd like to look at which denominators are available and then work on those. One denominator to play with could stem from the poles you get from a speaker element, the box and a DC blocking cap. Then I'd do the same thing with the other element(s) in the speaker, then, if necessary, increase the filter order, and end up with a denominator that I split in two (for two-way speakers) for linear summation.

Each of the two numerators is then modified digitally so that the product of the digital filter and the naturally occuring electromechanical phenomena, make the sum of the two numerators equal to their common denominator. And that should give a linear phase system.

With my speaker knowledge I don't know how the element and box work together and whether or not a DC blocking cap is needed.

Any opinions?

Regards,
Børge

#### gfiandy

If you have filtered the LF out of the tweeter output there is no need for a DC block capacitor unless the amplifer is single ended (quite unlikley). In fact one of the significant improvements of active filter set up is that the amlipfier is directly coupled to the speaker so it has much better control of the drive unit.

Unfortunately I don't know enough about digital filters to be able to comment on your concepts. I can say is that it is very inportant to use dither in any stage that requantizes the signal even if it seems the quantization noise would be too small be of concequence. I was involved in some comercial work on this and it is amazing how far down the signal needs to be before you can not hear it. To save processing power I know some systems sub sample the bass driver so its processing is not so power intensive.

I think you will struggle to implement this in an FPGA as most comercial designs used dedicated DSP chips. However I don't know the FPGA you are using or how efficient your algorithms might be.

One problem I can see you running into is, speakers have an acoustic roll off which will afffect the phase response quite a way from the point they actually start rolling off. So even if you come up with a perfect electrical solution you may find that when you apply it to your speakers the phase is all messed up and they don't sum correctly.

Really you need to simulate using the actual drive unit measurements and your proposed transfere function. Unfortunately I don't know a way to do this maybee some one else can suggest something.

Sounds like a really intersesting project.
Best of luck,
Andrew

#### borges

Andrew,

I was hoping to use DC coupling in my source and amplifier and put the DC blocking after any potential source of DC. But if this has a strong negative effect on impedance and "drivability" I'll have to reconsider.

I plan to use dithering all over the place. This far I've used FIR filters but for IIR it is important to use horrendous resolution and dithering.

The reason I started out with FPGAs was that I'd have 100% control over all digital IO. And the distributed arithmetic (FIR) filter Xilinx provides was a no-brainer. (But the state machine driving it was not I like the ability to choose arbitrary resolutions and Verilog's implicit parallel execution.

That said, I'm moving from the clean and square digital world to the realm of actual, physical masses moving around. The speaker roll off you mention is part of the denominator I plan to use in the filter design.

So what I'd like is to understand the physics and express the roll-off due to acoustics, element mass, cabinet geometry, element impedance etc. as an analog filter. When I can express this, that's when the fun begins for me!

Cheers,
Børge

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