Hi
It seems to me that this kind of combination is rare. ASRC chips are often used with DS dac chip but not the multibit chip. Is there any particular reason? I am wondering how multibit DAC chip would sound with an ASRC in front of it.
I know multibit chips are old but why not exploring this?
Has anybody tested this scheme?
Cheers
It seems to me that this kind of combination is rare. ASRC chips are often used with DS dac chip but not the multibit chip. Is there any particular reason? I am wondering how multibit DAC chip would sound with an ASRC in front of it.
I know multibit chips are old but why not exploring this?
Has anybody tested this scheme?
Cheers
1) Nobody make multibit DAC chips anymore....
2) ASRC are bad anyway, so why ruin a multibit DAC....
Why would you want to do this? Perhaps ASRCs are used with DS DAC chips because they're jitter sensitive? Multibit can't be improved by adding ASRC IMO.
ASRC can indeed diminish incoming jitter (as classicaly examplified by the benchmark DAC1).
They also make things easy since we only have to provide one very good system clock for the whole range of incoming digital signals. One can then be a lot more relaxed about the timing coming out of the various digital receivers.
We can also guarantee that the DAC chipset will work at its optimal point.
Finally, the analog filter after the DAC is a bit relaxed in its requirements since we can always feed a 96 or 192khz signal into a digital filter rather than a 44.1khz or 48khz one.
In my experience, a well implemented ASRC is in practice sonically transparent. So if your implementation of a multibit DAC doesn't benefit from the points above there's no reason why it should be better or worse with an ASRC thrown in.
They also make things easy since we only have to provide one very good system clock for the whole range of incoming digital signals. One can then be a lot more relaxed about the timing coming out of the various digital receivers.
We can also guarantee that the DAC chipset will work at its optimal point.
Finally, the analog filter after the DAC is a bit relaxed in its requirements since we can always feed a 96 or 192khz signal into a digital filter rather than a 44.1khz or 48khz one.
In my experience, a well implemented ASRC is in practice sonically transparent. So if your implementation of a multibit DAC doesn't benefit from the points above there's no reason why it should be better or worse with an ASRC thrown in.
I will give it a try. I have ordered a board with an src4392 chip. I will feed my tda1541a dac with 4fs i2s signal from the src4392 and report back. still waiting for the shipment.
when using as a standalone dac fed by spdif through cs8414 receiver I believe can hear distortion in high frequency due to jitter. transport is a modded ps audio lambda which is supposed to have pretty low jitter.
based on the specifications of some asrc chips I think they should be transparent enough although I know bit perfect may be lost.
when using as a standalone dac fed by spdif through cs8414 receiver I believe can hear distortion in high frequency due to jitter. transport is a modded ps audio lambda which is supposed to have pretty low jitter.
based on the specifications of some asrc chips I think they should be transparent enough although I know bit perfect may be lost.
It really depends on your circuit. I just installed a SRC4192 between Ian's SPDIF board and FIFO. I need to increase the FS (44.1K->192K) to make LPF simple. It does a good job here. BTW, my chip is AD1860 multibit DAC.
PS.There is also AK4137 which is 768k capable.
PS.There is also AK4137 which is 768k capable.
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Rare? They used to be the rage with SPDIF-input DACs during a time when USB was limited to 48kHz/16-bit.
But now the audiophiles have turned their focus to locally generated clocks and asynchronous* USB, while denouncing the evils of ASRC^ and jitter.
*Actual components used may or may not actually be asynchronous
^The actual multibit DAC used may or may not work at the same sampling rate as the input signal.
But now the audiophiles have turned their focus to locally generated clocks and asynchronous* USB, while denouncing the evils of ASRC^ and jitter.
*Actual components used may or may not actually be asynchronous
^The actual multibit DAC used may or may not work at the same sampling rate as the input signal.
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I have not actually seen of heard about any commercial CDP or DAC that include both multibit DAC and ASRC chip.
For DIY projects, ASRC is obviously going opposite direction with NOS topology and therefore often dismissed?
Most multibit DACs are decades older than ASRC chips. I think that's the reason ASRC is usually pair up with new DACs which also happened to be Delta- Sigma design.
Not sure if I'm on the same page...
To me, multi-bit delta-sigma DACs, like CS4398 and AD1852, are... well... multi-bit delta-sigma.
Reading between the lines this time, I guess people are using the term to refer to R2R DACs? Then yea there's no reason to use ASRC with those.
To me, multi-bit delta-sigma DACs, like CS4398 and AD1852, are... well... multi-bit delta-sigma.
Reading between the lines this time, I guess people are using the term to refer to R2R DACs? Then yea there's no reason to use ASRC with those.
Not rare but not common either. Just past their time. The Teac Esoteric D3 and VRDS 25 are two examples.
Many years ago, I built an experimental DAC which utilized both the AD1896 ASRC chip, and the AD1865 (the one Audio Note uses in it's DACs) 18-bit D/A chip. ASRC chips essentially function as digital reconstruction filters, with the side-benefit of strong jitter suppression. I noticed nothing particularly special about their combined sound. The DAC sounded pretty much like most other multibit DACs commonly featuring a non-asynchronous half-band digital reconstruction filter.
As has been pointed out, I think that one reason you don't see this combination of functions togther in commercial DACs is because multibit D/A chips were being phased out of production roughly around the time that decent ASRC chips were becoming commonly available. I suspect another reason is that the jitter suppression potential of ASRC didn't fully become appreciated until even later. I can't readily think of any reason to employ ASRC in a consumer DAC unit other than for it's jitter suppression potential. A typical synchronous oversampling brickwall digital reconstruction filter otherwise performs the same function as ASRC at much lower complexity.
As has been pointed out, I think that one reason you don't see this combination of functions togther in commercial DACs is because multibit D/A chips were being phased out of production roughly around the time that decent ASRC chips were becoming commonly available. I suspect another reason is that the jitter suppression potential of ASRC didn't fully become appreciated until even later. I can't readily think of any reason to employ ASRC in a consumer DAC unit other than for it's jitter suppression potential. A typical synchronous oversampling brickwall digital reconstruction filter otherwise performs the same function as ASRC at much lower complexity.
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Thanks all for the useful insights. It seems that many people complain about spdif interface being jittery. Yet many dacs do not address this issue.
Using an ASRC after spdif receiver seems to be much more simple than other solutions such as slaving the transport or diy a PPL.
I have not heard the AN DAC but it doesn't seems to have done anything much to address the jitter issue with spdif connection.
Using an ASRC after spdif receiver seems to be much more simple than other solutions such as slaving the transport or diy a PPL.
I have not heard the AN DAC but it doesn't seems to have done anything much to address the jitter issue with spdif connection.
It's quite a strange design by TEAC to put an ASRC chip in a CDP. It make more sense in a separate DAC.
Was reading up on ASRC, there are many setting of HI or LO.
How would one set these configurations?
Does the setting HI / LO relate to ground or whether it sees resistance?
I was trying to set the master clock of a ASRC fromm fs256X running at 11.2m to 512x so that i can useva Crystek 957 in place of a XO in an attempt to lower jitter.
Thanks
How would one set these configurations?
Does the setting HI / LO relate to ground or whether it sees resistance?
I was trying to set the master clock of a ASRC fromm fs256X running at 11.2m to 512x so that i can useva Crystek 957 in place of a XO in an attempt to lower jitter.
Thanks
Hi,
Which asrc are you referring to? As for AK4137, HI= Vcc, LO= GND. The problem is usually the correct XO for your need. I found most datasheets are very confusing at this part.
Did you experiment with running the AD1865 at differing clock rates I wonder? Just curious if you had any listening experience of the same chip but run faster/slower.
I am intending to feed both dac and asrc with the same superclock output.
I read through all datasheets and It is possible to select either 16bits, 20 bits, 24 bits etc...
Now sampling rate of the old dac chip is 44.1, fs256 and is I want run the ASRC at 88.2k, but this would mean I will have reset the dac chip to x512 instead of x256in order to use the higher frequency of the higher sampling rates.
It has to be done by reprogramming eith dac or ASRC to run of just 1 frequency, and use the internal counters of the chips to acheive this instead of adding say a 74hc163.
This means I will have to set the mclk values but cannot figure how to set the different combinations of HI /LO to achieve this.
I read through all datasheets and It is possible to select either 16bits, 20 bits, 24 bits etc...
Now sampling rate of the old dac chip is 44.1, fs256 and is I want run the ASRC at 88.2k, but this would mean I will have reset the dac chip to x512 instead of x256in order to use the higher frequency of the higher sampling rates.
It has to be done by reprogramming eith dac or ASRC to run of just 1 frequency, and use the internal counters of the chips to acheive this instead of adding say a 74hc163.
This means I will have to set the mclk values but cannot figure how to set the different combinations of HI /LO to achieve this.
With differing ASRC output sample rates, yes. However, the output sample rate in effect 'programs' the polyphase FIR filter cut-off frequency - which shifts proportionally with the ASRC chip's output sample/clock rate. This changing filter cut-off frequency potentially calls into question any subjective sound quality differences heard versus the output sample/clock rate.
That said, I didn't notice any definitive subjective differences until the output sample rate was low enough to produce an polyphase filter cut-off within the audio band - narrowed only by 500Hz. Intriguingly, a slightly in-band cut-off produced sound that lost most of what I would call digital glare, leaving a much more natural and relaxed sound. I never did verify whether the glare was lost merely due to the frequency domain sacrifice of 500Hz of the upper band edge, or maybe because of the removal of the A/D converter's anti-alias filter impulse response already encoded on the CDs - sort of a linear-phase apodising filter, per Peter Craven.
Actually it is a cs4192, believe the settings for selection of bit/sample rates are similar of dacs and ASRC's.
But not certain how exactly it is done.
It is not detailed how one can go about setting these, except for HI/LO or ON/OFF.
Ground and vcc, but vcc may need a resistor?
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