Mosfet threshold temperature coefficient

This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.
Various mosfet amplifier designs like the SKA150 and the IRF240/9240s make attempts to compensate for temperature.
I found this ST application note which shows how process decisions strongly affect the coefficient
The data sheets are usually very vague about behaviour at low currents.

I measured a Fairchild FQA46N15 and found 8mV/K at 5mA, 7mV/K at 10mA Ids. This is much greater than a bipolar transistors 2mV/K

This means that these mosfet designs will be very sensitive to supplier and process changes.

I am reasoning that a mosfet with a tab temperature of 40C in a 20C environment will have a much higher die temperature than one at 40C in a 30C environment - this error is made worse by using large heatsinks, where the die to casing thermal resistance becomes more significant
Okay, ingenue question. Those numbers are negative, right? BJT temperature is negative 2 so the voltage drop Vce decreases as it warms up? Or is that just the diode drop B-E decreasing?
So NFET decrease voltage drop V source to drain in the conduct state as they warm up by even more than BJTs?
BJTs Vbe and vertical mosfets Vgs both have negative temperature coefficients and need a compensation circuit to adjust the Class AB bias as things warm up.
Lateral mosfets conveniently have a zero coefficient at typical quiescent currents.

What I am finding is that vertical mosfets vary a lot depending on their production process, my Fairchild part is roughly double that of the Device1 part in the ST application note
Good somebody does some experimental science.
I replaced a .39 ohm wirewound emitter resistor below an output bjt with a ~.40 resistance Fairchild NFET to kill a turn on cross current surge with a RC timer. With the fet on the same heatsink, maybe that is a stupid idea due to thermal runaway, this says.
Hexfets used in AB need a modified Vbe multiplier. I use a BD139 mounted on the output devic and operating at just on 3.5 Vce in series with a 4.7V 400mW zener, which is mounted on the pcb but NOT on the output device. A 100uF electro is across both Vbe mult and the zener. This seems to work extremely well, starting around 125mA cold at 20C over ambient the quiescent is around 115mA. This seems about right to me.
May I ask you a question?
You could faff around with the coefficient - I have done this myself - but finally you have to build and test on your Fairchild mosfets. The big test is cold to hot on a working amp.

I use Fairchild mosfets. Remember that your coefficient must be doubled, since you are using a complementary pair from a single bias generator. The source resistor modifies the final implementation, too. Try it, you will be saved a lot of long work.......
Last edited:
I am planning to find something with better stability. The greater the temperature coefficient, the more likely the die is to get a hot spot and blow in a linear amplifier. Also it is more likely that I will end up with transient underbias.
P channel and N channel are not automatically the same either. It is very frustrating that the datasheets mostly don't show any Vgs data below 1A
I plan to test Vishay and Infineon asap.
One thing is clear, unless you go to extraordinary levels to match devices, multiple output pairs will only have one pair conducting at quiescent. The source resistor forces sharing at high currents only
Two smaller devices in parallel rather than one big device on the same heatsink means that I have a better measurement of actual die temperature.
It is an interesting simulation problem to see what happens to the distortion spectrum when the pairs are not perfectly matched, I would not like to guess which is best
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.