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- Thread starter Diogo
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look at this site:

http://www.irf.com/technical-info/appnotes.htm

Likely Application Note AN-944 contains the information You`re

searching for.

particular condition (it varies dynamically) and then

use the relation:

1 amp * 1 second = 1 volt * 1 farad

of course you will be scaling this to pico or nano farads

The volt figure will be the Vgs difference you are

charging that capacitance to.

An example?

I = 1 V * 1 nF / 10 uS

I = 1 * 10^-9 * 10^5

I = 10^-4

I = .1 mA

Somebody let me know if I make a math error here.

There are two important capacitances for driving MOSFETs; Ciss and Crss. Ciss is the lumped input capacitance; Crss is the miller feedback capacitance.

Ciss is the stated input capacitance; this is the combination of Cgs (capacitance gate to source) and Cgd (capacitance gate to drain), with the caveat that Cgd is measured at a fixed voltage per JEDEC specs, 25 volts VDS.

Why is that important? While Cgs is essentially a fixed capacitance, Cgd is highly variable; it's a depletion capacitance dependent on the gate to drain voltage, and behaves much the same as a diode junction capacitance. It can vary over a wide ratio, between 10 and 20 to 1 depending on the device technology. It's generally fairly low at VDS=25 volts and up (though it does decrease further with increasing voltage), but as the drain voltage falls toward the gate voltage, it increases dramatically. This is a source of increased HF distortion if you use vertical DMOS transistors as amplifiying elements with signal swings on the drain close to the gate voltage. This is why running relatively high voltage circuits either single ended or complementary (say, with 30-50V rails), and staying away from anywhere near "clipping" these circuits produces much better results.

In the case of a true class A linear amplifier, the MOSFET acts as more as an integrator; there isn't very much change in the gate voltage, and the gate behaves much the same as in the plateau region for switching current source loads (the classic gate charge test, also described in data sheets from most FET manufacturers, including IR and Infineon. In this case, the gate charge required is the Qgd for the voltage swing required acrosss the relatively low gate to drain capacitance; the Cgs component of the input capacitance isn't hardle exercised, because the gate voltage is nearly constant. You can get a rough estimate of this from the data sheet, because Qgd charge is usually presented for two values, 20% of rated Vgs and 80% of rated Vgs. However, this includes the high capacitance region- if you avoid that, you in the much more linear area.

In this case, a good estimate comes from subtracting the 20% Qgd from the 80% Qgd, and multiplying this by two (you're not just turning on, your traversing a sine wave), then calculate the current for the time intervale for the highest frequency you want to be able to reproduce. So, if you have any of those pesky SACD's, you might want to size your driver to be comfortable with gate drive for frequencies up to 50 kHz at full output, perhaps a little higher. The headroom can't hurt, unless it forces you to compromise on a device selection or operating point somewhere else.

Best regards,

Jon

What is the big diferrence betwen mosfets and bjts, I know that the driving current is much lower in mosfet and with the same rails the bjt delivers more power, but besides that, there is any other big difference?

Excluding the gate stoppes, why not change directly a bjt for a mosfet considering thet the drive current would be more than needed.

Sorry about these questions but I am only an student, and I am sure that I'm asking some stupid questions, but there is no one else to help me with that, and I have no access to a good book here in Brazil they are rather expensive.

Biasing is rather different for FETs vs BJTs. For one thing, the voltage needed to get meaningful bias current flowing gets lower with increasing temperature for a BJT, but rises for a FET. For this reason, very high power amplifiers ( > 500 W ) often use FETs, because it is hard to track the temperature of the output devices well enough to make sure that they don't get too much bias, which would heat them up, decreasing the bias requirement, heating them more, and so on, until they self destruct.

Although bipolar devices draw base current, the base current can be made less important by using Darlington connections or other sorts of buffering. Bipolar devices also have a capacitance that acts like Cgs of a FET; you can calculate it Cpi = (1/2piFt)*(Ic/Vt) where Ft is the transition frequency of the transistor (you might be able to find this in its data sheet), Ic is the collector current, and Vt is the thermal voltage, about 25 mV at room temp and increasing proportional to temperature.

So an interesting result is, if you have a 50 MHz Ft bipolar device with 1 ampere of current flowing in it, at room temperature, the capacitance you have to control is about 127 nF. This is the equivalent of a lot of FETs.

Again, by using darlingtons or other buffers you can make this less significant, but you can see that FETs probably have several advantages in terms of ease of drive circuits.

That said, some designers favor BJTs, claiming they are more linear. They DO tend to have lower output impedance for the same current flow.

Bipolar devices also have a capacitance that acts like Cgs of a FET; you can calculate it Cpi = (1/2piFt)*(Ic/Vt) where Ft is the transition frequency of the transistor (you might be able to find this in its data sheet), Ic is the collector current, and Vt is the thermal voltage, about 25 mV at room temp and increasing proportional to temperature.

So an interesting result is, if you have a 50 MHz Ft bipolar device with 1 ampere of current flowing in it, at room temperature, the capacitance you have to control is about 127 nF. This is the equivalent of a lot of FETs.

[/B]

Now, that seems a little strange. Would Ic be the actual collector current or the Ic that Ft is specified at? To the best of my knowledge, C_CB is a function of V_CB, not I_C. It is also a function of the transistor chip design, so I doubt that one formula would be able to cover this for any transistor.

Just as an example, my favorite Sanken output transistors 2SA1303/2SC2837 have a C_CB of 110 resp. 60 pF at 80V, which is a lot lower than 127 nF! Admittedly, these Sanken parts have exceptionally low capacitance, but other power transistors are maybe an order of magnitude higher at the most.

Eric

You may want to double-check the arithemetic, but I think 127 nF is correct.

There are two parts of capacitance between the base and emitter.

One part is directly voltage dependent, like Cbc, and its value at zero voltage is often referred to as Cje.

I was referring to the other one, the small-signal diffusion capacitance. It is always there, in any bipolar transistor, (or in any forward biased PN junction, for that matter) and its size is essentially determined by the effective base width, and by how long it takes the carriers to cross the base region.

It depends on the actual current flowing in the transistor, and on the effective base width with that current flow.

The length of time it takes a carrier to traverse the base region is called the "transit time" Tf of the transistor. So if there is a collector current Ic flowing in the device there is an amount of charge Ic*Tf in the base.

The capacitance is the derivative of this charge with respect to voltage. The current is related to the base-emitter voltage by a relationship

Ic = Is*exp(Vbe/Vt)

where Vt is the thermal voltage kT/q. The derivative of Ic vs Vbe works out as Ic/Vt.

So the capacitance due to current flow in the transistor, is

Tf*(Ic/Vt).

Note that this is a really weird "capacitor", because it gets a lot smaller while you discharge it, and a lot bigger as you charge it. So it doesn't imply a charge storage of C*V, just that incremental changes in base-emitter voltage result in corresponding incremental changes in base charge.

The actual base-emitter capacitance will be slightly higher, due to the extra voltage dependent term that is not due to charge storage effects.

1 Cap between gate and drain.

2 Cap betweeen gate and source and since you have a source follower to cap gets smaller with higher load impedance (I'm not online here with the expression for this, help me, high gm is good here)

3 All of these caps are very unlinear!

Calculate 2-10 nF for the whole output stage. You must have at least 10 mA and 50 mA will be sufficient I think.

10mA into 10 nF gives you a slew rate of 1 V/µs. I/C=Slew rate (A, F, V/s is the units)

The best you can do is to test in real life as Nelson suggests.

capslock said:This makes more sense to me, but I'll have to think about it. Why would one worry about C_BE? After all, it is more like a bootstrap, isn't it? And it might be the cause for local oscillations.

Eric

You should worry even for Cgs because it is "not small" and also very unlinear.

Ground rule (grundregel in swedish?? or maybe basic rule?): Use sufficient amount of output devices, not too many, not too few.

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