MOS-FET input capacitance

I'm designing power amplifier with HEXFETs and I don't know how much current do I need to drive 12 paraell devices.
I use simple formula - I=2*pi*f*V*C or I=SR*C
where f-frequency, V-voltage rms, C-capacitance od device.
So when I look to datasheets I see 3 capacitances 1. Input capacitance, 2. Output Cap. and 3. Reverse transfer cap. So when I'm using device as source follower I have to count with reverse transfer cap (kick me if I'm not true, please). Reverse transfer cap depends on Vds, and here I want to put a question - What is the right cap. to count with, resp. which one do you use (that one in datasheet, or do you look to graph).
This question maybe looks stupid for you, but if you count with IRF640N
C at 25V 53pF
C at 1V 700pF

current at 100V/us
53pF 0.5mA
700pF 70mA

MOSFETs are easy to drive at DC. It's a little tougher at the high end of the audio band!

Since Vgd is always changing, you have to plan for the worst case, or your amp will be slew rate limited. Is that a single-ended or push-pull output stage? If it's single-ended, you're looking at 8.4 nF of capacitance. Push-pull should reduce that considerably - by not quite half - since half the FETs will be at a high Vgd when the other half are at minimum Vgd.

But since you should rarely encounter those conditions on actual music, you should have quite a bit of headroom.

Don't discount Cgd so quickly. If you are pulling any appreciable current, you will also have a few volts swing on the gate drive. Nelson Pass pointed out the other day that Ids is essentially a linear function of gate charge. Your drivers also have to handle that C load.

Nelson Pass

The one and only
Paid Member
2001-03-29 12:38 am
This is a difficult one because the interaction of the
three capacitances are not all that simple in a linear
output stage. The elephant on the dance floor is
Cgs, but fortunately the voltage variation across that
is much smaller than the output signal.

To give you a practical value, 12 IRFP240's will slew
something like 20-30 V/uS with about 10 mA
of gate current. If you bias the stage prior to the
MOSFETS at 20 mA, you will probably get those
kind of numbers, and you will note that these are
similar to your estimate.

I said "Don't discount Cgd so quickly..." but I was thinking Cgs. I hope the context makes that clear. Mr. Pass's comments come from experience, so you should definitely believe him before me!

Where Cgd comes into play is in common-source stages... and there it's the dominant capacitance because of Miller effect. Cascodes help a lot in this application.
Thank you Mr.Pass for your reply, because I was trying to drive these MOS-FETs with high current and then I had problems with heat in resistors, which caused distortion. Now I know that I don't need too high current to drive FETs ( I used 0.6A RMS ).

Also thanks to all that have replyed.