Ultra low THD is usually a very exciting area as most designers balance between zeros and oscillation, for some of these amplifiers all it takes is a sneeze from either the listener or the playback to set it off, even the weather can set it off, once you power it on, it whispers into your ear 'say somethn', hopefully morpheus will play nice
Morpheus Vs Orchestra , you choose 143.76mm*132.08mm, use own BOM (files provided for non commercial purposes for researchers, curious onlookers, audiophiles and diyers)
Bias @130mA
https://www.pcbway.com/project/shareproject/Morpheus_audio_power_amplifier_61fe3f69.html
Morpheus Vs Orchestra , you choose 143.76mm*132.08mm, use own BOM (files provided for non commercial purposes for researchers, curious onlookers, audiophiles and diyers)
Bias @130mA
https://www.pcbway.com/project/shareproject/Morpheus_audio_power_amplifier_61fe3f69.html
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at least 100watts 150 volts, depending on taste the other ultra low THD approach is here https://www.pcbway.com/project/shareproject/ORCHESTRA_POWER_AMPLIFIER_fce54e63.html
You could change the compensation scheme to knock in an extra zero, the voicing will change towards clarity in the highs
Any ideas on going lower, the math works, the bias is anything 130mA and above for the quasi complementary output stage, if the VAS is already CFP why didn't I go full CFP output stage which requires lower bias current?
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For these results C12 and C13 have been bypassed. Measured implementation results will vary as were exploiting error cancellation in the feedback loop, in some implementations there may be no measurable distortion , devices are MJH11022 or 2SD2560
I understand some of the paralleled devices are for doubling/tripling current in the current mirrors but are all of them necessary/significant?
.asc file please ! I am particularly interested in the spice directives you use to get those clean THD graphs !
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The simulated 1W/4R THD is useless. The noise contribution will be 1000 times of the THD. Also, any 0.0000x simulation that is not confirmed by measurements on a real amp is also useless.
The simulations: such low noise floor but such a wide fundamental. The simulation has 150 dB resolution, yet the fundamental has a skirt a few 100Hz wide - cant sound good... but it's there and you can't say its lack of resolution...
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The width of the peak depends on the window function and how many cycles fit in the FFT input buffer, nothing to do with the signal.
If you use many more signal cycles per FFT, and more bins in the FFT, you'll get much narrower peaks. Here's a great resource about the subtleties of the FFT (there are many): https://holometer.fnal.gov/GH_FFT.pdf
If you use many more signal cycles per FFT, and more bins in the FFT, you'll get much narrower peaks. Here's a great resource about the subtleties of the FFT (there are many): https://holometer.fnal.gov/GH_FFT.pdf
Don't read too much into the noise floor. The noise floor in an FFT is proportional to the FFT bin width. Increase the FFT length (-> smaller bins) and watch the noise floor drop.
The simulation does show that the amp is not fundamentally broken ... assuming that it's able to produce a 20 Hz to 20 kHz sine wave into a 4-8 Ω load and has reasonable slew rate in simulation that is. I wouldn't pop open the champagne just yet, but it seems worthwhile to prototype the amp.
I'm not surprised that doubling up on the devices degrades performance. Usually a lower current density in a BJT results in worse performance.
How much loop gain does this amp have at DC and at 20 kHz?
Tom
The simulation does show that the amp is not fundamentally broken ... assuming that it's able to produce a 20 Hz to 20 kHz sine wave into a 4-8 Ω load and has reasonable slew rate in simulation that is. I wouldn't pop open the champagne just yet, but it seems worthwhile to prototype the amp.
I'm not surprised that doubling up on the devices degrades performance. Usually a lower current density in a BJT results in worse performance.
How much loop gain does this amp have at DC and at 20 kHz?
Tom