JLH steering output transistor base current, ignoring output voltage and current.
(except in the GNF loop, after the paralleling). Seems a fairly compatible topology
for parallel abuse. Certainly with the 74LS04, as you got 120 ohms extra insurance
built into each output totem.
Could piggyback a dozen or more if you could figure a way to get the heat out...
PNP Collector pulldown must be proportionally smaller the more gates you drive.
Sim a dumbed down inverter logic gate in LTSpice is not the same, and it does
not work in this application. You need the full internal schematic to understand
why the input has to be pulled down.