JAT501 simulated using TINA TI and possible improvements

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Hi all,

I have been following John Audio Tech youtube channel for a while now and it has a lot of fun projects including this JAT501 amplifier. I have decided to put it together in a simulator to learn little more about amplifiers as a process. It has been fun to play with different inputs and examining what parts of circuit does what.

Another goal was to run Fourier series analysis in the sim to see what kind of distortion it might produce.

I really like the choice of output transistors - 2SC5200 and 2SA1943.
Was able to load those spice models from official website no problem.
Also using green LED model from Cordells website spice library.
All other components are default in TINA TI library.

Attached all files.
 

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By adding few transistor I think there is a way to improve on THD figures more.
Distortion reduced 10x
Main changes in attached schematics are using emitter follower in VAS and reducing the gain to 10x.
BD140 BD139 driver transistors were replaced with KSA1381 and KSC3503.
Current sharing resistors reduced to 0R1 value.
Miller capacitor reduced to 47p
Driver transistors current increased to 10mA
VAS current increased to 10mA
LTP CCS green LED replaced with transistor
 

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Added inclusive compensation to the VAS stage. Reduced distortion to 0.0015%.

Overall, by adding one transistor EF for VAS and inclusive compensation (resistor and cap), THD can be reduced by a lot.

Note this is a simulation and real life figures can be different.

As always, attached
 

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This made for stability. (below) Decoupling the driver/predriver and B-C shunting with 22pF .
Badger was EF2 , not enough current gain to need extra compensation.
EF3 is 100K+ Hfe , local FB loop on rails needs to be be broken - R/C works well.
You also have to slightly cripple the predrivers with 22pF caps.
It is a X100 improvement over a EF2. BTW , just attaching 3 stages without the" extras" - will oscillate ! I did it !

PS - below is 1K OPS's on DIYA. Surprised Chinese have not stole it.

OS
 

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ok here is v3
don't know how to setup those currents between them three... did 2.5 mA and twice as much around 5mA for the first two
just used 5200 1943 since already loaded models
 

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With simulators you need to skip the transient period before starting the measurement. For that give generous 100 cycles by appointing 0.1s for 1khz. Tina will not like it, insist.
I go 10 (delay) cycles on my LT. delay cycle is what skips on LT.
What is cool , I've noticed the real world (Wolverine) actually outperforms my LT simulations.
Sims can't take layout into account.
OS
 
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ok here is v3
don't know how to setup those currents between them three... did 2.5 mA and twice as much around 5mA for the first two
just used 5200 1943 since already loaded models
For THD Sampling Start Time =1. Ignore error.

You will have some BIAS problems with 3 EF stages. Not so easy to solve in reality...

Check square signal transient - there is some ringing.

R4, R5 - values are too high I think.

...
 
It usually plays out with a simple Vas expect .01 to .05% THD at 1 kHz
and adding Beta Enhancement will be .001 to .004 %

With a simple Vas usually you need 2ma or even 3ma for differential input
to be able to drive the Vas and get decent high frequency.
Unfortunately high current in the Differential increases instability.

With improved Vas differential usually only needs 2ma and usually stability
will be rather good with small amount of degen.

Getting the Differential down to 1ma will be even more stable
and could be possible with all TO-92 Vas and cascode.

Problem is the parts count for this topology is rather high to get the usual
.001 % distortion. And With compensation to keep it stable at high Frequency.
Dont expect more than usual .01% to .05% or lower at 20 kHz

Doing a very simple model , and comically tossing in a diode
bias string LOL. This classic topology below will perform same results
or better, with tremendous reduction in parts count.
Second gain stage could be TO-92 with EF3 output.
Differential 1ma current which keeps it rather stable
and 2nd gain stage stays cool around 4.5ma
With EF3 output could likely get 2nd gain stage down to
2 or 3ma and just use faster T0-92 transistors

HITACHI_SIMPLE_EF2.JPG
1686236999368.png
1686237047407.png


You can delay sample start time to 1 sec but 100u is all needed to fluff results
 

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Here is revised v2 of improved schematics.
I think I finally got this thd sim right this time lol. used 100u value
Paralleled output transistors should allow for PSU voltage of up to 48V and power of 290W ??? into 4 ohms
two pole compensation reduces distortion from 0.0040 to 0.0011

Not sure how to do bode plot to see the phase margin
did not do step response either

This is really JAT801 since output transistors are in parallel.
 

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