A voltage input is converted to current by R10, fed to the resistors R8 and R7 which convert back to voltage to drive the lateral MOSFET gates. The inner quad Q1/2/3/4 is like a translinear loop and serves to set the bias as well as cancel the Vbe drops of Q3/Q1 on the signal path.
Some local feedback via R11 serves to increase linearity somewhat, but the driver stage can be opamp-based as the signal swing needed into R10 is about 10V and 20mA peak.
The current-mirror style cascode transistors Q5/Q6 serve to keep the dissipation in Q/1/2/3/4 all low to reduce self-heating.effects.
I haven't investigated real-world thermal stability of the configuration yet, but it should be possible to do that at low voltage without output devices since R7 and R8 are current driven, which is rather convenient - next step is choosing a breadboard to stripdown and reuse, mine are all full ATM!
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It is an inverter actually. Symmetrical triplet current mirrors, the reference legs (Q4-Q2) are bound to ground and the diode legs (Q3-Q1) are the inputs, modulated by the input signal through R10 on the emitters.
The node R10-R3-R4-R11 act thus as a virtual ground in this setup, input impedence is a little better than R10. R11 is fundamental for stability of this stage.
Not seen as far as I can remember; maybe something alike it does exist.
The node R10-R3-R4-R11 act thus as a virtual ground in this setup, input impedence is a little better than R10. R11 is fundamental for stability of this stage.
Not seen as far as I can remember; maybe something alike it does exist.
Unless these 2SJ49C/2SK134C's are new-born remakes of those well-known Hitachi veterans, this topo can't be that new, me thinks 😉.
Best regards!
Best regards!
🙂
Though I'm just using them as generic lateral FET models, prototyping will probable use ECX10x20 devices.
Indeed it inverts, the way I've modelled the driver is an inverting opamp, and before that a non-inverting opamp as input stage, both using global feedback:
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Curious to see a double or forked feedback loop. I'm not sure if this is stable.
U1 and U2 act as integrators, so open loop gain for both with different hf-corners (C1, C2).
If it proves less stable then expected (the fb loops can fight each other), you can choose to connect R15 to R10 and R13 to the output for 'spread' feedback, or use U1 in a classic inverter (R13 to R10) and single overall feedback (R15 to outp).
Did you run AC analysis and a plot to show?
Also, to find DC instabilities, try to simulate power startup (V1 & V2 equal but opposite up from zero to 50 in 0.1 steps). This shows how the output behaves, current in load (protection!?!) and response internally in the loopgain of the amp. Does it keep control and converge to its nominal setpoint or is it oscillating down to the setpoint?
Thermal stability can be simulated, but has limited value (reality is more brutal).
U1 and U2 act as integrators, so open loop gain for both with different hf-corners (C1, C2).
If it proves less stable then expected (the fb loops can fight each other), you can choose to connect R15 to R10 and R13 to the output for 'spread' feedback, or use U1 in a classic inverter (R13 to R10) and single overall feedback (R15 to outp).
Did you run AC analysis and a plot to show?
Also, to find DC instabilities, try to simulate power startup (V1 & V2 equal but opposite up from zero to 50 in 0.1 steps). This shows how the output behaves, current in load (protection!?!) and response internally in the loopgain of the amp. Does it keep control and converge to its nominal setpoint or is it oscillating down to the setpoint?
Thermal stability can be simulated, but has limited value (reality is more brutal).
