I'm attempting to design a class d amplifier with a half bridge setup. I was wondering if anyone knew if the IR2011 gate driver would be able to drive two IRFB4019 MOSFETS. Thanks
Given: N-Channel MOSFET
VGS = 10V
t (transistion) = 25nsec
Find: Gate drive current, IG.
From the MOSFET manufacturer’s specifications, QG = 50nC at
VGS = 10V. Using IG = QG/t(transition):
IG = QG/t(transition) = 50 x 10-9/25 x 10-9 = 2.0A
I drove 2 irfp240's in a class d amplifier with no problems.
25ns means 40MHz freq. = 2A I think this is correct.
if your fsw = 400KHz its switching time is 2.5us so it will take only 20mA current
the same i do with IRFP250 no problem
Simple answer: The COM pin on the IR2011 must connect to the source lead of the low side mosfet, ie the negative rail, in your case -18V and then the IR2011 Vcc need to be 12-15 volts above the negative rail.
When I remove the capacitor I get an overload on the -15v voltage rail, it pulls down the voltage to around 9 and tries to put an amp through. The positive rail is fine. My guess is that this may be caused from the relationship of Vb and Vs? I'm not sure if I'm understanding the datasheet correctly, right now still have Vb tied to Vcc (ground) but looking at the datasheet I don't think this should be the case, should Vb instead be tied to the positive voltage rail?
Alright so after a long day of reading and tweaking our design we have an open loop circuit running at the moment and the sound is surprisingly clear without the feedback loop. Basically what we did was tie both the FETs and the gate driver to the same power supply at -7 volts and +8 volts. This was due the fact that we were having issues when we tied two PSU's together.
We have COM/lowside FET at -7 volts and Vcc/highside FET at 8 volts. This put us at 15 volts above the negative rail but not quite Vb = Vs +10 (though I still don't think I am understanding that correctly). I'm in the process of drawing up a full schematic of our circuit to give the details of the rest of the changes which contains our previous stage as well.
I did notice that the lowside FET was getting warm to the touch. We are still testing on the circuit to see if this increases with time. We're still a little uneasy leaving the circuit on for an extended period of time after a long day of working on it, thinking we might have missed something.
I just wanted to thank everyone for the help so far as well as Reactance for the suggested reading!