Hi,
I plan to feed a SRC4192 from a MCU with I2S.
My master clock for the audio part is currently planned to be 24.576MHz. I chose this to be able to run the DAC with 128fs on the 192 kHz upsampled signal from the SRC4192.
Now I am wondering how I should clock the I2S signal that goes into the SRC4192 from the MCU. Does the SCK on I2S have to be a multiple (or even a 2^n factor) of the signals sampling rate (Fs). This would be a problem when having 44.1kHz Fs and only having a 24.576MHz clock.
Would I have to add a second clock just to create the SCK for the I2S->SRC4192 line in case of 44.1kHz playback?
Regards
I plan to feed a SRC4192 from a MCU with I2S.
My master clock for the audio part is currently planned to be 24.576MHz. I chose this to be able to run the DAC with 128fs on the 192 kHz upsampled signal from the SRC4192.
Now I am wondering how I should clock the I2S signal that goes into the SRC4192 from the MCU. Does the SCK on I2S have to be a multiple (or even a 2^n factor) of the signals sampling rate (Fs). This would be a problem when having 44.1kHz Fs and only having a 24.576MHz clock.
Would I have to add a second clock just to create the SCK for the I2S->SRC4192 line in case of 44.1kHz playback?
Regards
Yes, the 4192 will generate a new clock based on the on-board clock. So for the 44.1K family you will need a 22.xxxx clock. The 24.576 is only good for the 48K family.
You can feed any sample rate and the asrc will resample into the new sample rate...
You can feed any sample rate and the asrc will resample into the new sample rate...
So it's common to have two seperate clock circuits to support all common sampling frequencies?
Also one more question: When I take a 22.xx MHz clock for the 44.1kHz and I would want to use a SCK of 64fs, how would I do the clock division ideally?
Also one more question: When I take a 22.xx MHz clock for the 44.1kHz and I would want to use a SCK of 64fs, how would I do the clock division ideally?
One more thing: When I install an additional 22.5792 MHz oscillator on my board and I want to do a 64fs bitclock on I2S when running 44,1 kHz, would I use a binary divider to generate the bitclock, or are there any better choices?
Actually I might even be able to install a 2,8224 MHz oscillator which matches exactly the bitclock for 44.1 kHz transfers.
What do you think would be the better choice?
Actually I might even be able to install a 2,8224 MHz oscillator which matches exactly the bitclock for 44.1 kHz transfers.
What do you think would be the better choice?
It is probably not common to have two clocks, but it is a requirement if you want to support both 44.1 and 48K families. I don't know how fs is generated (you will have to look at the data sheet to figure this out). I only have experience with the Metronome module from twistedpearaudio.
Since you are familiar with microprocessors, why not use the 4193 which has a s/w interface? And then use dual frequency clocks where you can choose the frequency with a pin.
Also, according the asrc theory (the little I know) converting to an integer multiple of the sample frequency would not be any different than converting to fractional multiple of the sample frequency...
Since you are familiar with microprocessors, why not use the 4193 which has a s/w interface? And then use dual frequency clocks where you can choose the frequency with a pin.
Also, according the asrc theory (the little I know) converting to an integer multiple of the sample frequency would not be any different than converting to fractional multiple of the sample frequency...
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