Hi All,
I'm working on a reasonably affordable AD-DSP-DA PCB for use in speakers with Hypex NCxxxMP amplifier modules.
Currently I'm stuck at the I2S clocking part of the schematic.
I'm planning to use a ADAU1452 DSP as master, supplying BCK and LRCK to 1x AK5572 AD and 3x AK4490 DA. Considering cost vs. specifications I have found the Crystek CCHD-575-25-24.576 oscillator to be suitable.
The ADAU1452 has a MCLK input and a CLKOUT output that can drive MCLK to multiple IC's. CLKOUT is after a PLL and devider/multiplier. The only spec Analog Devices gives about the CLKOUT output signal quality is a cycle to cycle jitter of between 12-109ps. This is worse than what the Crystek oscillator can do, so it would make sense to me to directly supply MCLK from the crystal to the AD and DA IC's.
LRCK, BCK and Data out will still be clocked through the ADAU1452 with it's jitter. I think those should then be reclocked to the Crystek to improve jitter. Sofar I've seen two methods, using FIFO buffering or using flip flops. The former is too complex and expensive for me, so that leaves the latter. One thing I wonder about the flipflop method; is it possible for a data edge to jitter right before/after a clock edge, causing some data edges to be missed for one cycle?
Will this topology work, and will it be an improvement over routing I2S straight between AD-DSP-DA?
Is the flip flop reclock method the way to go?
I'm hoping for some pushes in the right direction. All suggestions, pointers on anything that I've got wrong/missed will be welcome.
Thank you for taking your time to read my post and/or reply.
Parts that I'm planning to use:
AD: AK5572
DA: AK4490EN
DSP: ADAU1452
Clock: Crystek CCHD-575-25-24.576
Opamps: LM4562
Opamp + supply: LT3045
Opamp - supply: LT3094
Other supplies: LP38798
I'm working on a reasonably affordable AD-DSP-DA PCB for use in speakers with Hypex NCxxxMP amplifier modules.
Currently I'm stuck at the I2S clocking part of the schematic.
I'm planning to use a ADAU1452 DSP as master, supplying BCK and LRCK to 1x AK5572 AD and 3x AK4490 DA. Considering cost vs. specifications I have found the Crystek CCHD-575-25-24.576 oscillator to be suitable.
The ADAU1452 has a MCLK input and a CLKOUT output that can drive MCLK to multiple IC's. CLKOUT is after a PLL and devider/multiplier. The only spec Analog Devices gives about the CLKOUT output signal quality is a cycle to cycle jitter of between 12-109ps. This is worse than what the Crystek oscillator can do, so it would make sense to me to directly supply MCLK from the crystal to the AD and DA IC's.
LRCK, BCK and Data out will still be clocked through the ADAU1452 with it's jitter. I think those should then be reclocked to the Crystek to improve jitter. Sofar I've seen two methods, using FIFO buffering or using flip flops. The former is too complex and expensive for me, so that leaves the latter. One thing I wonder about the flipflop method; is it possible for a data edge to jitter right before/after a clock edge, causing some data edges to be missed for one cycle?
Will this topology work, and will it be an improvement over routing I2S straight between AD-DSP-DA?
Is the flip flop reclock method the way to go?
I'm hoping for some pushes in the right direction. All suggestions, pointers on anything that I've got wrong/missed will be welcome.
Thank you for taking your time to read my post and/or reply.
Parts that I'm planning to use:
AD: AK5572
DA: AK4490EN
DSP: ADAU1452
Clock: Crystek CCHD-575-25-24.576
Opamps: LM4562
Opamp + supply: LT3045
Opamp - supply: LT3094
Other supplies: LP38798
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A one or two stage D-Flip Flop reclocker could probably work to clean up each ADAU1452 I2S output. Perhaps of of interest if considering such a design: EE552. Advanced Logic Design and Switching Theory. Metastability. Ashirwad Bahukhandi. (Ashirwad Bahukhandi) - PDF Free Download
Probably a good idea to build a prototype and carefully measure timing of ADAU1452 relative to the Crystek Clock to make sure a D-FF can reliably capture input I2S timing and help avoid any potential metastabilty issues.
Also, a lot depends on how you are planning to implement the system. Will the dacs operate at one sample rate only using the ASRC in ADAU1452 to resample incoming audio to one fixed sample rate for DSP and dacs? If so, what sample rate would that be?
Probably a good idea to build a prototype and carefully measure timing of ADAU1452 relative to the Crystek Clock to make sure a D-FF can reliably capture input I2S timing and help avoid any potential metastabilty issues.
Also, a lot depends on how you are planning to implement the system. Will the dacs operate at one sample rate only using the ASRC in ADAU1452 to resample incoming audio to one fixed sample rate for DSP and dacs? If so, what sample rate would that be?
Thank you very much Mark, that paper was what I needed to clear up my thoughts about what I now know is called metastability.
Although the outputs might contain less jitter after a synchronizer, I don't really like the idea that some bits might be incorrect because of the possibility of a metastable first stage.
It seems the best situation would be where ''by coincidence'' the ADAU1452 data edges are in between the Crystek clock edges already. The synchronizer would then hopefully never get metastable, with the help of the ADAU1452 PLL.
I think I will start this off by scoping a previous ADAU1452 design I did. The clock in to data output shift should be similar.
The AD-DA converters will run at multiples of 48kHz, up to 768kHz should be possible, but I understand the high samplerates makes the possibility of metastablility larger. I will most likely end up at 96kHz, or at 192kHz if I can get away with it. The analog I-O will be the main focus, the AD-DA converters will run synchroniously. The SPDIF input will also be used, but I'm willing to take compromise there. SPDIF in will be run through the ADAU1452 ASRC. I have to admit I haven't thought much about the SPDIF part yet though, ideas are welcome 🙂.
Although the outputs might contain less jitter after a synchronizer, I don't really like the idea that some bits might be incorrect because of the possibility of a metastable first stage.
It seems the best situation would be where ''by coincidence'' the ADAU1452 data edges are in between the Crystek clock edges already. The synchronizer would then hopefully never get metastable, with the help of the ADAU1452 PLL.
I think I will start this off by scoping a previous ADAU1452 design I did. The clock in to data output shift should be similar.
The AD-DA converters will run at multiples of 48kHz, up to 768kHz should be possible, but I understand the high samplerates makes the possibility of metastablility larger. I will most likely end up at 96kHz, or at 192kHz if I can get away with it. The analog I-O will be the main focus, the AD-DA converters will run synchroniously. The SPDIF input will also be used, but I'm willing to take compromise there. SPDIF in will be run through the ADAU1452 ASRC. I have to admit I haven't thought much about the SPDIF part yet though, ideas are welcome 🙂.
You don't need to reclock LRCK, BCK, or DATA for AK5572 (an ADC, so definitely not) or AK4490. The actual conversion is clocked by MCLK. You should switch to AK4493 if you are just getting started, I'm pretty sure it's nearly or exactly a drop-in replacement.
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Another vote for AK4493, it will sound better. On the reclocker issue, I would suggest try it and see what you think. If you don't think you need it after some careful listening, then you probably don't.
Thanks for your input Chris and Mark.
I measured the timings on a previous ADAU1452 project.
1 is ADAU1452 CLKOUT vs ADAU1452 BCLK out.
2 is Crystal direct out vs. ADAU1452 BCLK out.
Unfortunately I don't think this looks usable with a single flip flop reclock. I would need to delay Crystal direct out or ADAU1452 BCLK out in some way.
@chris719, is that also the case the the AK5572 as slave? Are LRCK, and MCLK only used to determine the rates but data syched to MCLK? I don't see this in the datasheet, could you share your source?
The AK4493 does look a bit better on paper. Not a drop in replacement, but very close. Have you guys compared it to the AK4490? Wondering if it is worth more than twice the price of the AK4490.
I measured the timings on a previous ADAU1452 project.
1 is ADAU1452 CLKOUT vs ADAU1452 BCLK out.
2 is Crystal direct out vs. ADAU1452 BCLK out.
Unfortunately I don't think this looks usable with a single flip flop reclock. I would need to delay Crystal direct out or ADAU1452 BCLK out in some way.
@chris719, is that also the case the the AK5572 as slave? Are LRCK, and MCLK only used to determine the rates but data syched to MCLK? I don't see this in the datasheet, could you share your source?
The AK4493 does look a bit better on paper. Not a drop in replacement, but very close. Have you guys compared it to the AK4490? Wondering if it is worth more than twice the price of the AK4490.
Sometimes people invert MCLK for clocking a reclocker D-FF, if needed. Doesn't usually matter what phase or inversion MCLK is relative to the I2S clocks and data.
I weer, is that purely to make use of the flipflop propagation delay? Or does it have other advantages?
If one chooses to add delay, the amount of added jitter from the delay circuit might be more than the added jitter of a simple inverter.
I don't think Mark understands your question here. Inverting the clock will still give you a setup time violation, yes, depending on the propagation delay of the inverter.
I am not 100% certain, but pretty close. On ADCs in general the data clocks mean nothing as far as conversion. There is always one clock that is critical for conversion; in this case it will be MCLK because it is the only clock you need in both DSD and PCM modes, and it makes sense because the modulator runs at very high speed. LRCK is only used to determine your final sample rate. In slave mode, there is no difference other than that you must provide BCK and LRCK that are synchronous to MCLK, instead of the chip dividing them down and driving those pins as outputs.
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Sorry, Mark is correct. I misread your post I think. Inverting the clock looks like it could work with the clock output directly since the falling edges are not occurring during transitions.
Ah I think I got it. So the idea is to invert the clock in order to shift the rising edge half a clock cycle right?