Help with Center DC Adjustment - Sansui B-2101

Hello everyone

I recently restored a Sansui B-2101 power amp and really tried hard.....
All caps were selected according to their specifications (low ESR, low leakage, etc.) The same values (left - right side) as possible and really the best quality (which was affordable for me). Transistors KQ 2-9 matched in pairs (as best as possible).
New thermal paste and everything you need to do a good job.

But today when comparing, I first noticed that there are errors in the SM. VR3,4 are shown reversed and the pin assignment on the 5-pin test point (picture 4-2. Top View) is different than in the picture next to the comparison table (2-2.). So far everything is still ok, since it was noticed early on.
The main problem, is the center dc 0V adjustment with VR2. There is no stable value to get. I have already exchanged the variable resistor for a 100 Ohm type because the fluctuations during the adjustment were too severe. However, I can only bring the voltage to around 0V and then the voltage starts to drift. The smallest changes on the controller let the voltage run away immediately. The adjustable range between +/- 200mV is only about a 10 degree radius.I can no longer imagine a solution.So here's my question to the real experts, is this possibly a design error or how can this happen? Is there possibly a solution that saves my day?

Attached are two pictures of the manual to understand what I'm writing about.
Thank you in advance for any help and have a nice day
Sansui madness.jpg


Sansui madness 2.jpg
 
board connection /solder issue somewhere.
or lead corrosion from glued parts
transistor might work or test ok but behavior is erratic from
age. offset relies on current sources to be stable.
or any diode/zener setting reference for sources
or transistors which maintain the current
 
Hi,

Is behavior the same on both channels? Same drifty phenomenon?

This power stage has a very unusual design. Note connection of R33, R34, R37, R38 and their path to ground. Make sure this path is intact.
The amp has DC coupling of bridge drive, i.e. flat gain to 0Hz; each side of the bridge as gain of 13.2 (eg. R28/R21). Each side of the bridge has the same gain, so total DC gain is 26.4. That will make the the amp more susceptible to drift issues than more typical designs that have unity gain biasing designs.

Because of the gain of 26, it's sensitive to any applied DC bias. So look carefully at the signal source at the emitters of Q6-Q7--- there's a convenient TP nearby and a pot to trim voltage to 0V. But study it's stability; its drift is multiplied by 26 and presented to the speaker terminals.
 
Hello and a big thank you to everyone involved.

Before that, the power amp was completely defective (the thick capacitors leaking, corrosion from the well-known adhesive and a defect on the power amp on the right...) and I wasn't able to do a test run.

That's why I tested all semiconductors and replaced them if necessary. The KQ2-9 renewed from my inventory (after matching). All plug connections are cleaned (with a fiberglass pen and the plugs with a part from my dentist🦷). All soldered connections checked and many resoldered. Almost newly built.....:unsure:
The "error" also occurs in both channels. All other parameters can also be adjusted to a tenth of a millivolt and remain stable.
The amplifier also runs great and sounds really fine, but.....I know that there is one value that is not correct
Tonight I will again take a close look at the resistors proposed by BSST and their connection and the transistors KQ4,5,6,7

I'll get back to you to let you know.

Have a nice and relaxed day and see you then
 
A follow up comment:

Your concern about adjustment stability seemed to focus on the centering adjustment in steps 3 and 4. I believe the stability in steps 1 and 2 is more pertinent because the amp uses bridge drive to the speaker; in effect, the voltage from each side to ground is a common-mode bias and is rejected, so should be less important. That said, I wouldn't be surprised if the differential measurement in steps 1 and 2 proves to be equally troublesome re stability.
 
@BSST

Thanks again for your very knowledgeable help!
I once again checked the path of the resistors to ground and put the transistors 2+4, 3+5, 6+8, 7+9 once again in pairs with new transistors. Then all other parameters (except in step 3-4) adjusted to the point. At step 3-4 again the same behavior.
However, I noticed that the structure of the board is a bit suboptimal, since there are two slightly thicker load resistors at the lower edge of the board, which emit heat that flows upwards. If I ventilated air onto the board from the back to the front with a fan, the whole thing behaved much more stable. Now I just bent the transistors inwards against each other so that they sit pretty close together, which also improved the behavior a bit.
I also noticed that the two varistors KD1,2 are very sensitive to heat and have different values. Is there a solution for these components that could be described as better?

Then a different question. The capacitances KC 11, 12, 13, 14 between the B-C connections of KQ 10, 12, 15, 16 is parallel to the Miller capacitance (which I thought was unfavorable because of the gain shift at higher frequencies), which circuit-related background does such a circuit form have?

Best regards and have a nice weekend
 
Then a different question. The capacitances KC 11, 12, 13, 14 between the B-C connections of KQ 10, 12, 15, 16 is parallel to the Miller capacitance (which I thought was unfavorable because of the gain shift at higher frequencies), which circuit-related background does such a circuit form have?

I'm guessing parallel the Miller capacitance you're referring to is internal to the transistors? Your comment is correct but the shunt caps are linear in contrast with junction capacitance within the semiconductors, so they mitigate somewhat. Such issues are the nature of the beast and I advise against playing with those compensation caps, as you would be flirting with possible oscillation. In any event, they would not have any effect on DC drift.

I also noticed that the two varistors KD1,2 are very sensitive to heat and have different values. Is there a solution for these components that could be described as better?

Those parts lie within the amp's feedback loop, so will have negligible contribution to offset drift.

I once again checked the path of the resistors to ground and put the transistors 2+4, 3+5, 6+8, 7+9 once again in pairs with new transistors. Then all other parameters (except in step 3-4) adjusted to the point. At step 3-4 again the same behavior.
However, I noticed that the structure of the board is a bit suboptimal, since there are two slightly thicker load resistors at the lower edge of the board, which emit heat that flows upwards. If I ventilated air onto the board from the back to the front with a fan, the whole thing behaved much more stable. Now I just bent the transistors inwards against each other so that they sit pretty close together, which also improved the behavior a bit.

So, back to the drift issue. Would you report how many mV of drift you observe differentially across the speaker terminals, i.e. the test in steps 1 and 2? Don't neglect to look at the DC present at Q6-Q7 emitters. A 100mV amp output offset can result from less than 4mV mV at that input.

With closer scrutiny of the schematic, I've discovered that the preamp stage from Q6,Q7 to input at JFET1 is also DC coupled with gain of 3.25. So the total DC gain from JFET1 to the speakers is 84.5 or nearly 39dB. IMHO, this is excessively large; just over 1mV of offset error at JFET1 will produce 100mV across the speaker. You will find that tweaking the VR1 pot near JFET1 will produce big changes at the speaker terminals.

A diagnostic test would lift the driven end of R43 and instead connect it to ground, say at board terminal 6. Then you'll be able to assess drift in the output stage independently from drift contributed from earlier stages. Again, I would attach little concern to the drift in the step 3/step 4 measurement. Error there only impacts centering of the common-mode bias which in turn has only minor effect on clipping amplitude; what matters most is undesired DC drift across the speaker.

It would be possible to introduce DC blocks in the amps if you are well skilled, but I hesitate to suggest.
 
@BSST

Hello and once again thank you for the technically interesting and helpful explanations!

As far as the shunt capacitor is concerned, I just wanted to know how it compares to the transistor's internal Miller capacitance ;)

If possible, I would like to leave the circuit design unchanged, since the developers must have had something really good in mind with this power amplifier.
I know you can always do better...usually. But since the structure of the design is quite complex and the components "do a lot" to each other, I will only do what is absolutely necessary.

I have now checked the voltage at the speaker output (VR3 ignored) and only changed JVR1 (Step 1,2). An increase of 1mV at the TP changed the voltage at the output by about 10mV.
If I adjust the voltage to exactly 0mV in step 1,2 and cause a change of 10-100mV with VR3, the voltage at the output only changes by a few mV.
Thanks for this tip!
I have now made 2 derivations from soaked hard cardboard over the load resistors, so that the heat can be dissipated on the right and left of the board. The drift now fluctuates constantly between approx. +/- 10mV (according to the manual +/- 5mV) and at the output there is only a change in the 0.1 mV range.
I can definitely live with that.
Thank you again for your explanation and the hint that this attitude is not really very important and that you have given my troubled soul absolution.
Thanks also to everyone else who may have already made an effort with my problem

Best regards from Germany and see you soon.....
 
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